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Interfacing I²C* Devices to SMBus Controller

White Paper: Determine how to interface I²C* devices and Intel® I/O Controller Hub SMBus controller with analysis guidelines. (Jan. 2009)

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Accessing Real Time Clock Registers and NMI Enable Bit

White Paper: Provides necessary steps and sample code to access Real Time Clock registers and NMI Enable Bit in I/O addresses 0x70-0x77. (Jan. 2009)

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Techniques for Debugging Packet Processing Systems

White Paper: Describes problems engineers face while debugging packet processing systems, with techniques for finding system errors. (v.1, Dec. 2009)

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Meeting Storage Demands for Home, SOHO, and SMB Customers

White Paper: Explains how SOC Intel® processors provide performance and cost-effectiveness for home, SBA storage solutions.

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Debugging Machine Check Exceptions on Embedded Intel® Architecture

White Paper: Step-by-step approach for debugging machine check exceptions on Intel® architecture platforms, with info on causes. (v.001, July 2010)

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Segmented Memory Protection on Intel® Microarchitecture

White Paper: Emphasizes aspects of the segmented memory protection mechanism on Intel® technology for improving performance. (v.1, Oct. 2011)

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Chimera—Expression Matching Engine with Full PCRE Semantics

White Paper: Chimera combines HyperScan with other matchers to deliver block mode scanning with full PCRE semantics. (v.1, Oct. 2013)

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Merge Enterprise Routing, Network Services on Intel® Architecture

White Paper: Enterprise benefits of service-rich software routing on single Intel® architecture, offering flexibility, scalability, and lower costs.

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Simplify Virtualized Network Elements in Telecom

White Paper: Tail-f* provides an abstraction layer between operations support systems and ISV software-based network elements. (v.3, August 2013)

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Going Beyond DPI Software on Intel® Architecture

Advanced cyber security and policy management runs on scalable, general-purpose hardware on Intel® Architecture.

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