PHY Interface for the PCI Express* Architecture: Revision .9
Revision .71 of the PCI Express 3.0 PHY Interface Specification defines the intended architecture for updating the PCI Express PHY Interface Specification to support PCI Express 3.0.
This revision includes support for PCI Express* implementations conforming to the PCI Express Base Specification, Revision 3.0.
The PHY Interface for the PCI Express Architecture (PIPE) is intended to enable the development of functionally equivalent PCI Express PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the PCI Express base specification rather than repeating its content. In case of conflicts, the PCI-Express Base Specification shall supersede the PIPE spec.
This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. This information should be viewed as guidelines for or ‘one way to implement’ base specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
Read the full PHY Interface Revision.
284KB
We are sorry, This PDF is available in download format only
PHY Interface for the PCI Express* Architecture: Revision .9
Revision .71 of the PCI Express 3.0 PHY Interface Specification defines the intended architecture for updating the PCI Express PHY Interface Specification to support PCI Express 3.0.
This revision includes support for PCI Express* implementations conforming to the PCI Express Base Specification, Revision 3.0.
The PHY Interface for the PCI Express Architecture (PIPE) is intended to enable the development of functionally equivalent PCI Express PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the PCI Express base specification rather than repeating its content. In case of conflicts, the PCI-Express Base Specification shall supersede the PIPE spec.
This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. This information should be viewed as guidelines for or ‘one way to implement’ base specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
Read the full PHY Interface Revision.
