PHY Interface For the PCI Express* Architecture
Revision .7 of the SATA 3.0 PHY Interface Specification defines the intended architecture for updating the PCI Express PHY Interface Specification to support SATA 3.0. This revision includes support for SATA* implementations conforming to the SATA Specification, Revision 3.0.
The PHY Interface for the PCI Express Architecture (PIPE) for SATA 3.0 is intended to enable the development of functionally equivalent SATA PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the SATA specification rather than repeating its content. In case of conflicts, the SATA specification shall supersede the PIPE spec.
This spec provides some information about how the MAC could use the PIPE interface for various SATA protocols. This information should be viewed as guidelines for, or "one way to implement" SATA specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
One of the intents of the PIPE specification is to accelerate SATA device development. This document defines an interface to which ASIC and device vendors can develop. Peripheral and IP vendors will be able to develop and validate their designs, insulated from the high-speed and analog circuitry issues associated with the PCI Express PHY interface, thus minimizing the time and risk of their development cycles.
Read the full PHY Interface Paper.
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PHY Interface For the PCI Express* Architecture
Revision .7 of the SATA 3.0 PHY Interface Specification defines the intended architecture for updating the PCI Express PHY Interface Specification to support SATA 3.0. This revision includes support for SATA* implementations conforming to the SATA Specification, Revision 3.0.
The PHY Interface for the PCI Express Architecture (PIPE) for SATA 3.0 is intended to enable the development of functionally equivalent SATA PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the SATA specification rather than repeating its content. In case of conflicts, the SATA specification shall supersede the PIPE spec.
This spec provides some information about how the MAC could use the PIPE interface for various SATA protocols. This information should be viewed as guidelines for, or "one way to implement" SATA specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
One of the intents of the PIPE specification is to accelerate SATA device development. This document defines an interface to which ASIC and device vendors can develop. Peripheral and IP vendors will be able to develop and validate their designs, insulated from the high-speed and analog circuitry issues associated with the PCI Express PHY interface, thus minimizing the time and risk of their development cycles.
Read the full PHY Interface Paper.
