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Transceivers: Arria II* Family Handbook, Vol 2

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Transceivers: Arria II* Family Handbook, Vol 2

Transceiver Architecture in Arria II* Devices

This chapter describes all available modules in the Arria II GX* transceiver architecture and describes how these modules are used. In addition, this chapter lists the available test modes, dynamic reconfiguration, and ALTGX port names.

Arria II GX devices provide up to 8 full-duplex clock data recovery-based transceivers with physical coding sublayer and physical medium attachment, and support the serial protocols.

Transceiver Block Overview

Arria II GX devices offer two to four transceiver blocks per device. Each block consists of four fully-duplex (transmitter and receiver) channels, located on the left side of the device (in a die-top view).

Clock Multiplier Units (CMU)

Each transceiver block contains two CMU blocks, which contain a CMU phase-locked loop that provides clocks to all the transmitter channels in the same transceiver block. These two CMU blocks can provide two independent high-speed clocks per transceiver block.

Read the full Transceivers: Arria II Family Handbook, Vol 2.