Celeron® M Processor 530 Datasheet Addendum
Addendum to Intel® Celeron® M Processor 500 Series for Mobile Intel® 945 Express Chipset Family Datasheet
This document is an addendum to the Intel® Celeron® M Processor 500 Series for Mobile Intel® 945 Express Chipset Family Datasheet.
The purpose of this addendum is to document the mechanical packaging and thermal features specific to the Intel Celeron M processor 530 and available only to Intel embedded customers. Please refer to the master Intel Celeron M Processor 500 Series Datasheet for all other specifications relating to this processor.
In this document, the Intel Celeron M Processor 530 will be referred to as the processor.
The following list provides some of the key features of this processor:
• Supported by the Intel 945 Express Chipset Family
• Single core
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache
• On-die, 1-MB second level shared cache with Advanced Transfer Cache Architecture
• 533 MHz Source-Synchronous Front Side Bus
• Supports Intel® Architecture with Dynamic Execution
• Data Prefetch Logic
• Supports both Micro-FCPGA and Micro-FCBGA packaging technology
• MMX, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental Streaming SIMD Extensions 3 (SSSE3)
Read the full Celeron® M Processor 530 Datasheet Addendum.