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How to Implement a 64B PCIe* Burst Transfer on Intel® Architecture

64B PCIe* burst transfer through the CPU core bus interface unit (BIU)

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How to Implement a 64B PCIe* Burst Transfer on Intel® Architecture

Executive Summary
To transfer data between two memory regions through PCIe* transactions, there are two alternatives:
• Through DMA configuration
• Through the core bus interface unit

In this paper, we focus on the second method and describe a way to transfer 64B of data in a single burst through the CPU core bus interface unit (BIU) to a memory region (outside of the CPU core and not part of cache hierarchy) reserved for a PCIe* device. The fundamental principle of this approach is to change the cache attribute of the PCIe* device memory region. With this approach, the I/O property of PCIe* memory is closely retained (no cache is used for retaining data on core) and a long burst PCIe* transfer is feasible. This method makes the best use of system bus and PCIe* bus bandwidth.

Read the full How to Implement a 64B PCIe* Burst Transfer on Intel® Architecture.