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Signal Integrity Pitfalls Upon Deviation From Intel® Guidelines

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Signal Integrity Pitfalls Upon Deviation From Intel® Guidelines

Background
Intel provides product Platform Design Guidelines (PDG) along with a fully validated Reference Board. Customers who design their boards exactly as the Reference board for any interface can use the SI Guidelines in the PDG, with no changes.

However customers working on Embedded Designs most often have to deviate from the PDG, since their designs can demand different layer stack ups or topologies, form factors etc. Hence they end up having to do their own simulations.

To design new solutions by simulation is tedious and can be very time consuming.

This document details the most often made deviations and the corresponding SI impacts to that interface.

Solution
This paper aims to provide an understanding of the SI impact when a deviation is made.

A thorough understanding of the SI impact can significantly help limit the simulation time by focusing only on the impact areas.

Read the full Signal Integrity Pitfalls Upon Deviation From Intel® Guidelines White Paper.