Supralinear Packet Processing Performance with Intel® Processors

We are sorry, This PDF is available in download format only

Supralinear Packet Processing Performance with Intel® Processors

Advances in semiconductor technology are making way for low-power multi-core processors. This transition enables embedded and communications applications to more broadly deploy systems with multiple execution cores due to the more favorable economic and thermal characteristics of this generation of processor technology.

This transition to multi-core processors promises more than an increase in the number of execution cores to increase computation capability. It offers additional flexibility for development and optimization of higher performance applications. In particular, multicore architectures can significantly improve program flow so that cache memory associated with each individual execution core is used more effectively. With multiple caches available to software developers, it is possible to optimize data locality driving higher cache-hit rates and improved overall application performance.

This paper describes the performance benefits that can be realized from the utilization of multiple processing cores for communications applications. The paper illustrates the programming concepts of pipelining and flow-pinning in a packet-processing application and presents performance results from the use of these techniques on a popular open source intrusion detection application. Using a real-world network traffic scenario with a high number of TCP connections, the results show supralinear (more than 6.2 times) performance improvements when IP traffic flows are distributed among four cores versus running the same application on a single core.

Read the full Supralinear Packet Processing Performance with Intel® Processors White Paper.