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Embedded Intel® Architecture Board Layout Checking GuideExecutive SummaryPrior to the fabrication, assembly, and power on of a board, a thorough review of the board layout is essential to meet the demands of time to market. In this document we will outline the “best practices” to guide the user through the process of doing an effective layout review. Aimed at the system engineer, this document will explain the process of how the layout review works in the lab and the required documents and reference materials for the review. This process includes inspecting the board, reviewing the power delivery, reviewing clocks, and reviewing the individual interfaces.IntroductionLayout of an board based on Intel® architecture is a very complex task. For the best results, it needs to be done by layout engineers with the help of system engineers and signal integrity engineers to provide a robust solution for all the interfaces on the board. However, since layout is the last stage before the board is sent to be built, it is critical to do a thorough check of a board layout.This white paper will talk in detail about important subsections in a board design, including: power delivery, system clocks, and other high speed interfaces—PCI Express*, SATA, and DDR to name a few.Read the full Embedded Intel® Architecture Board Layout Checking Guide White Paper.
Presents tips and steps for signal integrity simulation on a DDR interface.
Presents a signal integrity introduction and detailed steps for simulation on Intel® architecture.
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