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Readers of this application note will vary in familiarity with the subject matter from fairly new to those with a high degree of experience with it. This document assumes the reader is familiar enough with the IEEE Gigabit Physical Layer (PHY) test procedures to be able to recognize when an apparent test failure could be due to improper application of a test procedure and know how to re-check the setup and if necessary make appropriate adjustments and rerun it.
For readers just learning about IEEE Gigabit PHY conformance testing, this application note also provides information that includes checking test setups and measurement procedures where either or both are frequently found to cause false failure results as well as tips on the types of problems that can be caused by poor component choice or improper layout decisions. There is also some background information that many readers will know very well and can breeze over but the less experienced readers will find of interest.
This document describes steps to take when a failure is encountered during PHY conformance testing of an Intel® LAN-based design (though many of the principles could be applied to any LAN design based on the 802.3 specification). This knowledge can help a designer by saving the time it takes to call customer support and/or the time it takes for a support engineer to understand the system design, which frequently requires a schematic review and possibly a layout review later on during troubleshooting. For this reason, it is highly recommended that a designer consult this application note when a problem occurs during Gigabit PHY conformance testing.
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