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Intel® I/O Controller Hub 9M/82567LF/LM/V NVM: Map and Guide

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Intel® I/O Controller Hub 9M/82567LF/LM/V NVM: Map and Guide

Introduction

The document is intended for designs using a 10/100/1000 Mb/s Media Access Controller (MAC) that is integrated into an Intel® I/O Control Hub 9M (ICH9M) device in conjunction with an 82567LF/82567LM/82567V Physical Layer Transceiver (PHY).

The NVM space is used for hardware and software configuration. It is also read by software to determine and configure specific design features.

Unless otherwise specified, all numbers in this document use the following numbering convention:
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a suffix of “h” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).

NVM Programming Procedure Overview

The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS, Manageability Firmware, and a Flash Descriptor Region. It is programmed through the ICH9M. This combined image is shown in Figure 1. The Flash Descriptor Region is used to define vendor specific information, the location, allocated space, and read/ write permissions for each region. The Manageability (ME) Region contains the code and configuration data for ME functions such as Intel® Active Management Technology, ASF, and Advanced Fan Speed Control. The system BIOS is contained in the BIOS Region. The ME Region and BIOS Region are beyond the scope of this document and a more detailed explanation of these areas can be found in the Intel® I/O Controller Hub 9 (ICH9M) Family External Design Specification (ICH9M EDS). This document describes the LAN image contained in the Gigabit Ethernet (GbE) region.

Read the full Intel® I/O Controller Hub 9M/82567LF/LM/V NVM Map and Guide.