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Intel® 82598 Ethernet Controller Power Supply Design Clarification

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Intel® 82598 Ethernet Controller Power Supply Design Clarification

Introduction

This document describes the power supply sequencing and the Power On Reset (POR)/ LAN_PWR_GOOD design clarifications for the 82598 10 GbE controller.

Proper Power Supply Sequencing

The proper power on sequencing of the power supply voltage rails and the use of the internal Power On Reset (POR) versus the use of the externally generated LAN_PWR_GOOD signal (as specified in the current Intel® 82598 10 GbE Ethernet Controller Open Source Datasheet) are located in multiple sections of the document.

Consequently, all sections should be looked at for proper power on sequencing as well as the use of POR or the LAN_PWR_GOOD signal. Voltage rail sequencing must be followed (as described in the 82598 Datasheet) and as summarized below or excessive current leakage and/or device latch-up might occur. Intel has made several updates/clarifications to the Intel® 82598 10 GbE Ethernet Controller Open Source Datasheet, and recommends that designers follow the summary steps below to assure that the Intel® 82598 is properly initialized and does not subject the silicon to latch-up and/or forward biasing the internal ESD protection diodes.

Read the full Intel® 82598 Ethernet Controller Power Supply Design Clarification.