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Intel® 82575EB Gigabit Ethernet Controller: Design Guide

This document provides design data for specific features.

The 82575EB is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. For general information about this the 82575EB, see the device Datasheet.

Product documents referenced by this document include:
• Intel® 82575EB Gigabit Ethernet Controller Datasheet
• Intel® 82575EB Gigabit Ethernet Controller Manageability
• Intel® 82575EB Gigabit Ethernet Controller Software Developer's Manual (the SDM; includes the EEPROM data)
• Intel® 82575EB Gigabit Ethernet Controller Thermal Design Considerations

PCI Express (PCIe*) is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each port consists of a group of transmitters and receivers located on the same chip. Each lane consists of a transmitter and a receiver pair. A link between the ports of two devices is a collection of lanes. The 82575EB supports up to four lanes on the PCIe interface.

Each signal is 8b/10b encoded with an embedded clock. The PCI Express topology consists of a transmitter (Tx) located on one device connected through a differential pair connected to the receiver (Rx) on a second device. The controller may be located on the motherboard or on an add-in card using a connector specified by PCI Express.

The lane is AC-coupled between its corresponding transmitter and receiver. The AC-coupling capacitor is located on the board close to transmitter side. Each end of the link is terminated on the die into nominal 100 differential DC impedance. Board termination is not required.

Read the full Intel® 82575EB Gigabit Ethernet Controller Design Guide.

Intel® 82575EB Gigabit Ethernet Controller: Design Guide

This document provides design data for specific features.

The 82575EB is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. For general information about this the 82575EB, see the device Datasheet.

Product documents referenced by this document include:
• Intel® 82575EB Gigabit Ethernet Controller Datasheet
• Intel® 82575EB Gigabit Ethernet Controller Manageability
• Intel® 82575EB Gigabit Ethernet Controller Software Developer's Manual (the SDM; includes the EEPROM data)
• Intel® 82575EB Gigabit Ethernet Controller Thermal Design Considerations

PCI Express (PCIe*) is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each port consists of a group of transmitters and receivers located on the same chip. Each lane consists of a transmitter and a receiver pair. A link between the ports of two devices is a collection of lanes. The 82575EB supports up to four lanes on the PCIe interface.

Each signal is 8b/10b encoded with an embedded clock. The PCI Express topology consists of a transmitter (Tx) located on one device connected through a differential pair connected to the receiver (Rx) on a second device. The controller may be located on the motherboard or on an add-in card using a connector specified by PCI Express.

The lane is AC-coupled between its corresponding transmitter and receiver. The AC-coupling capacitor is located on the board close to transmitter side. Each end of the link is terminated on the die into nominal 100 differential DC impedance. Board termination is not required.

Read the full Intel® 82575EB Gigabit Ethernet Controller Design Guide.

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