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Intel® 82571EB/82572EI EEPROM: Information Guide Application Note

A series of 82571EB/82572EI EEPROMs are developed and validated as part of the 82571EB/82572EI validation effort. These dev_starter images represent a cross section of configurations that are available. Intel strongly recommends that designers use the dev_starter image. Dev_starter images have been fully validated with the reference design and can be used to ensure that the base functionality of a specific design is working as expected.Dev_starter images are developed using generic modules. Because some features are mutually exclusive, these modules are developed to preclude any generation of an EEPROM that has conflicting features. If a dev_starter image does not contain all the appropriate features that a specific design requires, please contact your Intel representative instead of modifying individual word or bit assignments to avoid conflicts.

The 82571EB/82572EI uses an EEPROM device to store product configuration information. The EEPROM is divided into three general regions:
• Hardware Accessed — Loaded by the Ethernet controller after power-up, PCIe* reset reassertion, in-band PCIe* reset, a D3 to D0 transition, a software commanded EEPROM read (CTRL_EXT.EE_RST), and a software reset (CTRL.RST, word 00000h, bit 26).
• Software Accessed — Used by software only. These registers are listed in this document for convenience and are only for software and are ignored by the Ethernet controller.
• Firmware Accessed — Used by BMC, PT, SPT, or ASF firmware.

Firmware Reset (all modes) - occurs after any of the following: LAN power up (LAN_PWR_GOOD assertion) Software-initiated firmware reset through a host command Software-initiated firmware reset through MAC CSRs Certain unrecoverable errors during manageability operation
Software-Initiated EEPROM Reload (ASF mode only) - occurs after any of the following: Software-initiated assertion of the SWSM.WMNG bit while manageability clock is off Software-initiated EEPROM reload through ASF register (asserting FR_RST.FRC_EELD or FRC_FLUSH) Software-initiated ERPROM reload through a host command System state transition S0 to S5 while ASF register bit CTL_PWRLS is cleared.

Read the full Intel® 82571EB/82572EI EEPROM Information Guide Application Note.

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