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Intel® 82559ER EEPROM Map and Programming Information

Intel® 82559ER EEPROM Map and Programming Information, 0.6

This document describes the EEPROM map and contents for products based upon the Intel 82559ER Fast Ethernet* controllers. Part of the EEPROM is used for hardware configuration, while part of the EEPROM space is read by Intel-supplied drivers and other configuration software to determine and configure features specific to that design. For compatibility, Intel does not create separate drivers for the 82559ER controllers.
EEPROM Device and Interface
The serial EEPROM stores configuration data for the controller. The EEPROM is a 3.3 volt 9346 or 9366 Microwire* device. The 82559ER supports 64-word sized EEPROMs. In PCI designs that do not use TCO functionality, the controller only requires an EEPROM that contains 64 registers of 16 bits per register. The 82559ER auto-detects the EEPROM size via a dummy zero mechanism following reset.
All accesses, read and write, are preceded by a command instruction to the EEPROM. The command instructions begin with a logical one as a start bit, two opcode bits (read, write, erase, etc.), and six bits of address. The address field is six bits for a 64 register EEPROM. The end of the address field is indicated by a dummy zero bit from the EEPROM. This indicates that the entire address field has been transferred to the EEPROM. A command is issued by asserting the EEPROM Chip Select (EECS) signal from the controller and clocking the data out of the EEPROM Data Input (EEDI) pin into the EEPROM on its data input pin relative to the EEPROM Shift Clock (EESK) controller output. The EECS signal is de-asserted after completion of the EEPROM cycle (command, address and data).

In designs employing 64-register EEPROM, the EEPROM read is approximately 6,000 clock cycles long (180 microseconds at 33 MHz). The system is required to provide a valid clock on the CLK pin for this time period after the de-assertion of RST#, even if the ISOLATE# pin is asserted (the CLK input is not isolated until the EEPROM accesses are complete). In designs employing 64-register EEPROM, the EEPROM read is approximately 6,000 clock cycles long (180 microseconds at 33 MHz). The system is required to provide a valid clock on the CLK pin for this time period after the de-assertion of RST#, even if the ISOLATE# pin is asserted (the CLK input is not isolated until the EEPROM accesses are complete).

Read the full Intel® 82559ER EEPROM Map and Programming Information, 0.6.

Intel® 82559ER EEPROM Map and Programming Information, 0.6

This document describes the EEPROM map and contents for products based upon the Intel 82559ER Fast Ethernet* controllers. Part of the EEPROM is used for hardware configuration, while part of the EEPROM space is read by Intel-supplied drivers and other configuration software to determine and configure features specific to that design. For compatibility, Intel does not create separate drivers for the 82559ER controllers.
EEPROM Device and Interface
The serial EEPROM stores configuration data for the controller. The EEPROM is a 3.3 volt 9346 or 9366 Microwire* device. The 82559ER supports 64-word sized EEPROMs. In PCI designs that do not use TCO functionality, the controller only requires an EEPROM that contains 64 registers of 16 bits per register. The 82559ER auto-detects the EEPROM size via a dummy zero mechanism following reset.
All accesses, read and write, are preceded by a command instruction to the EEPROM. The command instructions begin with a logical one as a start bit, two opcode bits (read, write, erase, etc.), and six bits of address. The address field is six bits for a 64 register EEPROM. The end of the address field is indicated by a dummy zero bit from the EEPROM. This indicates that the entire address field has been transferred to the EEPROM. A command is issued by asserting the EEPROM Chip Select (EECS) signal from the controller and clocking the data out of the EEPROM Data Input (EEDI) pin into the EEPROM on its data input pin relative to the EEPROM Shift Clock (EESK) controller output. The EECS signal is de-asserted after completion of the EEPROM cycle (command, address and data).

In designs employing 64-register EEPROM, the EEPROM read is approximately 6,000 clock cycles long (180 microseconds at 33 MHz). The system is required to provide a valid clock on the CLK pin for this time period after the de-assertion of RST#, even if the ISOLATE# pin is asserted (the CLK input is not isolated until the EEPROM accesses are complete). In designs employing 64-register EEPROM, the EEPROM read is approximately 6,000 clock cycles long (180 microseconds at 33 MHz). The system is required to provide a valid clock on the CLK pin for this time period after the de-assertion of RST#, even if the ISOLATE# pin is asserted (the CLK input is not isolated until the EEPROM accesses are complete).

Read the full Intel® 82559ER EEPROM Map and Programming Information, 0.6.

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