Intel® 82559 EEPROM Map and Programming Information, 3.0
Introduction and Scope
This document describes the EEPROM map and contents for products based upon the Intel 82559ER Fast Ethernet* controllers.
Part of the EEPROM is used for hardware configuration, while part of the EEPROM space is read by Intel-supplied drivers and other configuration software to determine and configure features specific to that design. For compatibility, Intel does not create separate drivers for the 82559 controllers.
EEPROM Device and Interface
The serial EEPROM stores configuration data for the controller. The EEPROM is a serial in/serial out device. The 82559 supports 64-word or 256-word sized EEPROMs,
In PCI designs that do not use TCO functionality, the controller only requires an EEPROM that contains 64 registers of 16 bits per register. The 256-register, (16 bits per register) EEPROM device is required in TCO enabled systems to store the heartbeat packet. CardBus systems require the larger EEPROM size to store the Card Information Structure (CIS). The 82559 auto-detects the EEPROM size via a dummy zero mechanism following reset.
All accesses, read and write, are preceded by a command instruction to the EEPROM. The command instructions begin with a logical one as a start bit, two opcode bits (read, write, erase, etc.), and six bits of address. The address field is six bits for a 64 register EEPROM. The end of the address field is indicated by a dummy zero bit from the EEPROM. This indicates that the entire address field has been transferred to the EEPROM. A command is issued by asserting the EEPROM Chip Select (EECS) signal from the controller and clocking the data out of the EEPROM Data Input (EEDI) pin into the EEPROM on its data input pin relative to the EEPROM Shift Clock (EESK) controller output. The EECS signal is de-asserted after completion of the EEPROM cycle (command, address and data).
Read the full Intel® 82559 EEPROM Map and Programming Information Application Note.