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Designing SERDES-SERDES Interfaces with the 82546GB Ethernet Controller Application Note (AP-466)

Design SERDES-SERDES Interface with Intel® 82546GB GbE Controllers


The goal of this document is to enable customers to construct a board layout design using the Serializer-Deserializer (SERDES) interface on Intel® Gigabit Ethernet (GbE) controllers. A typical application using the SERDES interface is GbE fiber design where the electrical interface connects to an optical module. However, another possible application would use the SERDES interface to drive and receive electrical signals over a backplane for board to board communication such as in modular servers. The benefit for using the internal SERDES for a backplane is that it reduces the cost, power and board size real estate of a design since neither optical module with associated fiber connectors nor copper PHY related components, such as magnetic and cable connectors, are required. Instead, the electrical signals are sent from the internal SERDES to traces that go to a backplane connection, then over a backplane and another backplane connector to the SERDES capable link partner for communication.

The use of SERDES is called out in many industry specifications. For example:
• IEEE 802.3z: Gigabit for fiber
• 1000BaseCX: Gigabit over 30 meters of 75 Ω coax cable
• 1000BaseX
• PICMG 3.1: Gigabit over 100 Ω differential backplane

Read the full Design SERDES-SERDES Interface with Intel® 82546GB GbE Controllers application note.

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