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Thunderbolt™ Technology for Developers [59 K]
Transforming I/O device interconnectivity and transfer performance, Thunderbolt™ technology enables flexible, innovative system design configurations.

Transforming I/O device interconnectivity and transfer performance, Thunderbolt™ technology enables flexible, innovative system design configurations.

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Universal Serial Bus Overview [58 K]
Overview provides information on Universal Serial Bus technology, including market growth, industry standards, wireless extensions, and future uses.

Overview provides information on Universal Serial Bus technology, including market growth, industry standards, wireless extensions, and future uses.

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Universal Serial Bus 3.0 and 2.0 Specifications [59 K]
Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.

Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.

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Wireless Host Controller Interface Specification [57 K]
The Wireless Host Controller Interface describes the register-level interface for a Host Controller for Wireless (USB) Revision 1.0.

The Wireless Host Controller Interface describes the register-level interface for a Host Controller for Wireless (USB) Revision 1.0.

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Enhanced Host Controller Interface Specification [58 K]
Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

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USB 3.0* Radio Frequency Interference on 2.4 GHz Devices
White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.

White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.

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Intel® QuickAssist Acceleration Technology for Embedded Systems [73 K]
Intel® QuickAssist technology helps the development community more easily integrate embedded accelerators in their designs.

Intel® QuickAssist technology helps the development community more easily integrate embedded accelerators in their designs.

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Advanced Host Controller Interface Specification [52 K]
The Advanced Host Controller Interface (AHCI) specification describes the register-level interface for a host controller for Serial ATA.

The Advanced Host Controller Interface (AHCI) specification describes the register-level interface for a host controller for Serial ATA.

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Intel® PRO/1000 PT Quad Port Server Adapter Product Brief
Product Brief: Intel® PRO/1000 PT Quad Port Server Adapter with 10/100/1000 Mbps connections for slot-constrained servers.

Product Brief: Intel® PRO/1000 PT Quad Port Server Adapter with 10/100/1000 Mbps connections for slot-constrained servers.

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Intel® 82563EB/82564EB Gigabit Ethernet Controllers: Product Brief
Product Brief: Intel® 82563EB/82564EB gigabit high-performance Ethernet Controllers offer support for Intel® I/O Acceleration Technology.

Product Brief: Intel® 82563EB/82564EB gigabit high-performance Ethernet Controllers offer support for Intel® I/O Acceleration Technology.

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EFI PCI Platform Support Specification v0.9
PCI platform Support Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code and basic components.

PCI platform Support Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code and basic components.

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PCI Express* (PCIe*) 3.0 Accelerator Features
Summary of PCI Express* capabilities for revision 3.0 accelerator features of the specification.

Summary of PCI Express* capabilities for revision 3.0 accelerator features of the specification.

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PCI Express* 3.0: Electrical Requirements for Designing ASICs
Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.

Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.

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PCI Express* 3.0: Optimize Device Architecture on Intel Platforms
Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.

Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.

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Benefits of PCI Express* Architecture for Components and Systems
White Paper: PCI Express* Architecture, benefits of designing components and systems.

White Paper: PCI Express* Architecture, benefits of designing components and systems.

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Why PCI Express* Architecture for Graphics?
White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

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PCI Express* Architecture [64 K]
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

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PCI Express* Architecture Power Management Rev 1.1
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

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PCI Express* Technology, Enterprise Serial Innovation
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

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PHY Interface For the PCI Express* Architecture
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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PHY Interface for the PCI Express* Architecture: Revision .9
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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PHY Interface for the PCI Express, SATA and USB 3.0 Architectures
Spec: Defines a set of PHY interface functions needed for PIPE compliant PHY. Also, outlines how the MAC could use the PIPE interface.

Spec: Defines a set of PHY interface functions needed for PIPE compliant PHY. Also, outlines how the MAC could use the PIPE interface.

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PHY Interface for PCI Express* and USB SuperSpeed Architectures
Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

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Designing Energy Efficient SATA Devices: 2011-2013 Platforms
Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.

Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.

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Serial ATA Host Controller Interface Spec: Contributor Agreement
Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

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