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RF CMOS Technology Scaling in High-k/Metal Gate Era
RF CMOS technology benefits from general CMOS technology scaling and improves by innovative transistor and interconnect technologies.

RF CMOS technology benefits from general CMOS technology scaling and improves by innovative transistor and interconnect technologies.

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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K
Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture
Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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Advanced Metal Gate/High-K Dielectric Stacks for CMOS Transistors
Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.

Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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High-κ Gate Dielectrics, Metal Gate Electrodes in Silicon and Non-Silicon Logic Nanotechnology
Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

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High-k/Metal-Gate Stack and Its MOSFET Characteristics
Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

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Evaluation/Transport Physics: Schottky-Gate III-V Compound Semiconductor QWFE Transistors
Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.

Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.

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High Performance 32nm Logic Technology
Record NMOS and PMOS drive currents are reported, along with the tightest contacted gate pitch for a 32nm or 28nm technology.

Record NMOS and PMOS drive currents are reported, along with the tightest contacted gate pitch for a 32nm or 28nm technology.

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Non-Planar, Multi-Gate InGaAs QWFETs with High-K Gate Dielectric and Ultra Scaled Gate-to-Drain/Gate-to-Source Separation
Paper: non-planar, multi-gate InGaAs QWFETs with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations of 5nm.

Paper: non-planar, multi-gate InGaAs QWFETs with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations of 5nm.

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First the Tick, Now the Tock: Intel® Microarchitecture (Nehalem)
White Paper discusses Intel® Microarchitecture (Nehalem), the basis for the Intel® Xeon® processor 3500 and 5500 series.

White Paper discusses Intel® Microarchitecture (Nehalem), the basis for the Intel® Xeon® processor 3500 and 5500 series.

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Introduction to Intel’s 32nm Process Technology
White Paper: Intel has been in high volume manufacturing on 32nm process technology with 2nd generation high-k + metal gate transistors since 2009.

White Paper: Intel has been in high volume manufacturing on 32nm process technology with 2nd generation high-k + metal gate transistors since 2009.

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Challenges and Innovations in Nano‐CMOS Transistor Scaling
Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.

Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.

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Embedded Intel® Architecture and High Speed Digital Design
White Paper: Board behavior of high speed digital signals and available design tools for embedded Intel® architecture products. (Jan. 2009)

White Paper: Board behavior of high speed digital signals and available design tools for embedded Intel® architecture products. (Jan. 2009)

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Tick, Tock: Next Gen Intel® Microarchitecture Nehalem
White Paper: Outlines next gen Intel® microarchitecture Nehalem benefits: scalability, power efficiency, and performance. (v.001, Apr. 2008)

White Paper: Outlines next gen Intel® microarchitecture Nehalem benefits: scalability, power efficiency, and performance. (v.001, Apr. 2008)

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Platform-Level Error Handling Strategies for Intel® Systems
White Paper: Provides platform-level error handling strategies and overview of error detection and notification capabilities. (v.001, May 2011)

White Paper: Provides platform-level error handling strategies and overview of error detection and notification capabilities. (v.001, May 2011)

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JTAG 101: IEE 1149.x and Software Debug
White Paper: Quick JTAG 101 overview of the various implementations and names of debug methods to help users migrate to IA32. (Jan. 2009)

White Paper: Quick JTAG 101 overview of the various implementations and names of debug methods to help users migrate to IA32. (Jan. 2009)

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An Introduction to the Intel® QuickPath Interconnect
White Paper: the Intel® QuickPath Interconnect links stitch together processors in distributed shared memory platform architecture.

White Paper: the Intel® QuickPath Interconnect links stitch together processors in distributed shared memory platform architecture.

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Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met
Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

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Presentation: RF CMOS Technology Scaling in High-k/Metal Gate Era
Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

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Gate Dielectric Scaling for CMOS
Presentation: SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.

Presentation: SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.

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Role of High-K Gate Dielectrics
Presentation Discusses Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices.

Presentation Discusses Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices.

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Fun Facts: Exactly How Small (and Cool) is 22 nanometers?
Intel introduces new 22nm technology.

Intel introduces new 22nm technology.

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Intel®’s 22nm Technology Moves Transistor Into the 3rd Dimension
Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.

Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.

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