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Gate Dielectric Scaling for CMOS
Presentation: SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.

Presentation: SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.

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Role of High-K Gate Dielectrics
Presentation Discusses Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices.

Presentation Discusses Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices.

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40nm InSb P-Channel QWFET for Low-Power Applications
Presentation: 40nm gate length InSb P-channel strained QWFET for low-power logic apps, including advantages, materials, and benchmarking.

Presentation: 40nm gate length InSb P-channel strained QWFET for low-power logic apps, including advantages, materials, and benchmarking.

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Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met
Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.

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Presentation: RF CMOS Technology Scaling in High-k/Metal Gate Era
Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

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RF CMOS Technology Scaling in High-k/Metal Gate Era
RF CMOS technology benefits from general CMOS technology scaling and improves by innovative transistor and interconnect technologies.

RF CMOS technology benefits from general CMOS technology scaling and improves by innovative transistor and interconnect technologies.

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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K
Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture
Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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Advanced Metal Gate/High-K Dielectric Stacks for CMOS Transistors
Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.

Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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High-κ Gate Dielectrics, Metal Gate Electrodes in Silicon and Non-Silicon Logic Nanotechnology
Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

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High-k/Metal-Gate Stack and Its MOSFET Characteristics
Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

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Evaluation/Transport Physics: Schottky-Gate III-V Compound Semiconductor QWFE Transistors
Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.

Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.

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Fun Facts: Exactly How Small (and Cool) is 22 nanometers?
Intel introduces new 22nm technology.

Intel introduces new 22nm technology.

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Intel®’s 22nm Technology Moves Transistor Into the 3rd Dimension
Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.

Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.

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Intel Global Manufacturing Facts
Fact Sheet: Intel Global Manufacturing

Fact Sheet: Intel Global Manufacturing

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EFI 1.10 Driver Writer’s Guide
Provides basic information for the most common classes of EFI drivers. Includes design guidelines for PCI, USB, and SCSI buses.

Provides basic information for the most common classes of EFI drivers. Includes design guidelines for PCI, USB, and SCSI buses.

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Challenges and Innovations in Nano‐CMOS Transistor Scaling
Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.

Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.

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Paper: 32nm Logic Technology for High Performance Microprocessors
Logic Paper: 32nm logic technology for high performance microprocessors

Logic Paper: 32nm logic technology for high performance microprocessors

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32nm Logic Technology with 2nd Gen High-k + Metal Gate Transistors
Presentation of 32nm logic technology for high performance microprocessors featuring 2nd generation high-k + metal gate transistors.

Presentation of 32nm logic technology for high performance microprocessors featuring 2nd generation high-k + metal gate transistors.

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Presentation: Low Power Optimize a 32nm SoC Platform Technology
Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

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Presentation: Low Power Optimize a 32nm SoC Platform Technology
Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.

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RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC App
Brief examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

Brief examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.

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High Performance 32nm Logic Technology
Record NMOS and PMOS drive currents are reported, along with the tightest contacted gate pitch for a 32nm or 28nm technology.

Record NMOS and PMOS drive currents are reported, along with the tightest contacted gate pitch for a 32nm or 28nm technology.

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