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Transforming I/O device interconnectivity and transfer performance, Thunderbolt™ technology enables flexible, innovative system design configurations.
Overview provides information on Universal Serial Bus technology, including market growth, industry standards, wireless extensions, and future uses.
Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.
The Wireless Host Controller Interface describes the register-level interface for a Host Controller for Wireless (USB) Revision 1.0.
Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.
White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.
Intel® QuickAssist technology helps the development community more easily integrate embedded accelerators in their designs.
The Advanced Host Controller Interface (AHCI) specification describes the register-level interface for a host controller for Serial ATA.
Product Brief: Intel® PRO/1000 PT Quad Port Server Adapter with 10/100/1000 Mbps connections for slot-constrained servers.
Product Brief: Intel® 82563EB/82564EB gigabit high-performance Ethernet Controllers offer support for Intel® I/O Acceleration Technology.
Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.
Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.
White Paper: PCI Express* Architecture, benefits of designing components and systems.
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.
Spec: Defines a set of PHY interface functions needed for PIPE compliant PHY. Also, outlines how the MAC could use the PIPE interface.
Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.
Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.
Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.