<Back to Content Library

Intel® E7505 Chipset

Intel® E7505 Chipset

The Intel® E7505 chipset takes full advantage of the Intel® Xeon® processors to deliver advanced technology and IO flexibility for both workstations and servers. The Intel E7505 chipset supports dual-processor workstation platforms optimized for the Intel Xeon processor with 533 MHz system bus and Intel NetBurst® microarchitecture. It combines 533 MHz system bus with faster memory speed, next-generation AGP 8X graphics, and improved I/O bandwidth for a comprehensive workstation platform.

 

Platform Features that Maximize Performance

  • Dual Intel® Xeon® processors with a 533 MHz system bus provide up to 4.3 GB/s of available bandwidth.
  • Dual DDR-266 memory channels provide up to 4.3 GB/s of memory bandwidth.
  • The direct attach AGP 8X port provides 2.1 GB/s of graphics bandwidth directly out of the MCH.
  • The Intel® Hub Interface 2.0 connection allows high-bandwidth I/O configurations; exceeding 1.0 GB/s of I/O bandwidth.

Product information

Features and benefits

Supports two Intel® Xeon® processors with 533 MHz system bus for dual-processing workstation platforms

Brings increased system bus performance and Hyper-Threading Technology of the Intel® Xeon® to workstations and servers.

533 MHz system bus capability

Supports a high-performance, balanced platform by enabling a 4.3 GB/s system bus bandwidth that can support greater memory, graphics and I/O bandwidths.

Dual-channel DDR266

Provides 4.3 GB/s of memory bandwidth for balanced performance on the Intel® Xeon® processor with 533 MHz system bus platforms.

Unbuffered or registered DDR memory

Allows design flexibility for diverse enterprise applications.

Memory Error Correction Code (ECC)

Memory error correction code for greater reliability.

Intel® x4 Single Device Data Correction (Intel®
x4 SDDC)

Allows continued memory operation in the event of a single device failure.

APG 8X Interface

Next-generation graphics interface, delivering 2.1 GB/s of graphics bandwidth directly from the MCH, for use with the most advanced AGP 8X graphics cards.

Intel® Hub Interface 2.0

Dedicated data paths for transferring greater than 1.0 GB/s of data to and from the MCH, which support I/O segments with greater reliability and faster access to high-speed networks.

Integrated high-speed USB 2.0

Six ports offer up to 40 times greater bandwidth over the original USB 1.1 for the most demanding I/O peripherals.

Alert on LAN* 2.0

Emits an alert in case of software failures or system intrusion, even when the O/S is not present or the system is suspended.

AC'97 controller

Supports Dolby* Digital 5.1 Surround Sound, delivering up to six channels of enhanced sound quality.  

Low-power sleep mode

Saves energy.

Additional information: 1 2

Technical Documents

View More >
Packaging information

Intel® E7505 Memory Controller Hub (MCH)

File Type/Size:  PDF 3523KB

 1005-pin Flip Chip-Ball Grid Array (FC-BGA)

Intel® 82870P2 64-bit PCI/PCI-X Controller Hub 2

File Type/Size:  PDF 1610KB

 567-pin Flip Chip-Ball Grid Array (FC-BGA)

Intel® 82801DB I/0 Controller Hub

File Type/Size:  PDF 6851KB

Intel® 82801DB I/O Controller Hub (ICH4) / Intel® 82801DBL I/O Controller Hub 4-L (ICH4-L)

Intel® 845GE/845PE Chipset Datasheet: Intel® 82845GE Graphics and Memory Controller Hub (GMCH) / Intel® 82845PE Memory Controller Hub (MCH)

 421-pin Micro Ball Grid Array (BGA*)

Product and Performance Information

open

1. Requires an Intel® Hyper-Threading Technology (Intel® HT Technology)-enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on the Intel® Core™ i5-750. For more information, including details on which processors support HT technology, visit www.intel.com/technology/platform-technology/hyper-threading/index.htm.


2. In a x4 DDR memory device, the Intel® x4 Single Device Data Correction (Intel® x4 SDDC), provides error detection and correction for 1, 2, 3, or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.