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Interrupt Swizzling Solution for Intel® 5000 Series based Platforms

Interrupt Swizzling Solution for Intel® 5000 Chipset Series

Introduction

Intel® 5000 Series Chipset supports PCIe devices attached to the MCH and/or the Intel® 631xESB / 632xESB I/O Controller Hub (including integrated PCIe* devices). Interrupt support for these PCIe devices is using PCI compatible INTx emulation scheme or using MSI/MSI-X scheme.

In case of INTx emulation scheme, the interrupts from the PCIe devices are signaled as inband messages that are eventually converted to system interrupts by the root complex. In order to better distribute INTx interrupts, the PCIe Base Specification 1.0a requires bridges to map interrupts from secondary side to primary side based on device number (per Table 2-13 of PCIe Base Specification 1.0a).

However, most ports have only one device with device number 0 that results in identity mapping of the interrupt (INTA f INTA, INTB f INTB,…). As a result, if root ports mapped the downstream interrupts messages as is to the interrupt controller, all PCIe interrupts will likely be mapped to a single input of the interrupt controller.

The Intel 5000 Series Chipset implements interrupt swizzling logic to rebalance and distribute the PCIe legacy interrupts for performance and load balancing. This document describes the interrupt swizzling scheme in detail and discusses the programming requirements to implement this scheme.

Read the full Interrupt Swizzling Solution for Intel® 5000 Chipset Series Application Note.

Interrupt Swizzling Solution for Intel® 5000 Chipset Series

Introduction

Intel® 5000 Series Chipset supports PCIe devices attached to the MCH and/or the Intel® 631xESB / 632xESB I/O Controller Hub (including integrated PCIe* devices). Interrupt support for these PCIe devices is using PCI compatible INTx emulation scheme or using MSI/MSI-X scheme.

In case of INTx emulation scheme, the interrupts from the PCIe devices are signaled as inband messages that are eventually converted to system interrupts by the root complex. In order to better distribute INTx interrupts, the PCIe Base Specification 1.0a requires bridges to map interrupts from secondary side to primary side based on device number (per Table 2-13 of PCIe Base Specification 1.0a).

However, most ports have only one device with device number 0 that results in identity mapping of the interrupt (INTA f INTA, INTB f INTB,…). As a result, if root ports mapped the downstream interrupts messages as is to the interrupt controller, all PCIe interrupts will likely be mapped to a single input of the interrupt controller.

The Intel 5000 Series Chipset implements interrupt swizzling logic to rebalance and distribute the PCIe legacy interrupts for performance and load balancing. This document describes the interrupt swizzling scheme in detail and discusses the programming requirements to implement this scheme.

Read the full Interrupt Swizzling Solution for Intel® 5000 Chipset Series Application Note.

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