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Intel E8500 Chipset external Memory Bridge (XMB) Datasheet

The Intel® E8500 chipset is a 4-way server chipset. The chipset is built architecturally around the Intel® E8500 chipset North Bridge (NB) and the eXternal Memory Bridge (XMB).

This document, the Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet, describes the features, modes and registers supported by the XMB component only. Additional details on the Intel® E8500 chipset North Bridge (NB) are provided in a separate document, the Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet. Contact an Intel field representative for Intel® E8500 chipset platform design information. For details on any other platform component, please refer to the component’s respective documentation. This chapter is an introduction to the entire Intel® E8500 chipset platform. Intel® E8500 Chipset North Bridge (NB) Feature List, the NB, is the center of the Intel® E8500 chipset architecture (refer to Figure 1-1). The NB provides the interconnect to:
• 64-bit Intel® Xeon™ processor MP via two 667 MHz system busses optimized for server applications
• XMB’s via four Independent Memory Interfaces (IMI)
• I/O components via one x4 and three x8 PCI Express* links and ICH5 via the HI 1.5 1.1.1 Processor System Bus Support
• Supports up to four 64-bit Intel® Xeon™ processor MP via two system busses.
• Supports dual system busses (2 processors per bus) for improved data bandwidth and frequency
• Operation at 166/333/667 MHz (Bus Clock/Address/Data)
• Maintains coherency across both busses
• Double-pumped 40-bit address busses with ADS every other clock which provides an address bandwidth of 167 million addresses/second total
• Quad-pumped 64-bit data bus providing a bandwidth of 5.3 GB/s per bus
• In-Order-Queue depth of 12
• Support for up to 32 deferred transactions per bus
• Deferred Phase support for out-of-order completion
• Supports ECC protection on data signals and parity protection on address signals

Read the full Intel® E8500 Chipset external Memory Bridge (XMB) Datasheet.

Intel E8500 Chipset external Memory Bridge (XMB) Datasheet

The Intel® E8500 chipset is a 4-way server chipset. The chipset is built architecturally around the Intel® E8500 chipset North Bridge (NB) and the eXternal Memory Bridge (XMB).

This document, the Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet, describes the features, modes and registers supported by the XMB component only. Additional details on the Intel® E8500 chipset North Bridge (NB) are provided in a separate document, the Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet. Contact an Intel field representative for Intel® E8500 chipset platform design information. For details on any other platform component, please refer to the component’s respective documentation. This chapter is an introduction to the entire Intel® E8500 chipset platform. Intel® E8500 Chipset North Bridge (NB) Feature List, the NB, is the center of the Intel® E8500 chipset architecture (refer to Figure 1-1). The NB provides the interconnect to:
• 64-bit Intel® Xeon™ processor MP via two 667 MHz system busses optimized for server applications
• XMB’s via four Independent Memory Interfaces (IMI)
• I/O components via one x4 and three x8 PCI Express* links and ICH5 via the HI 1.5 1.1.1 Processor System Bus Support
• Supports up to four 64-bit Intel® Xeon™ processor MP via two system busses.
• Supports dual system busses (2 processors per bus) for improved data bandwidth and frequency
• Operation at 166/333/667 MHz (Bus Clock/Address/Data)
• Maintains coherency across both busses
• Double-pumped 40-bit address busses with ADS every other clock which provides an address bandwidth of 167 million addresses/second total
• Quad-pumped 64-bit data bus providing a bandwidth of 5.3 GB/s per bus
• In-Order-Queue depth of 12
• Support for up to 32 deferred transactions per bus
• Deferred Phase support for out-of-order completion
• Supports ECC protection on data signals and parity protection on address signals

Read the full Intel® E8500 Chipset external Memory Bridge (XMB) Datasheet.

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