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Intel® E7500 Chipset MCH Intel® x4 SDDC: Application Note

The Intel® E7500 Chipset MCHs support Intel® x4 Single Device Data Correction (Intel® x4 SDDC). The x4 SDDC provides S4EC-D4ED (Single x4 Error Correction-Double x4 Error Detection). This document covers the implementation and validation specific to Intel® E7500 MCH.

Intel® Single Device Data correction (SDDC) algorithm
>The x4 SDDC is an ECC algorithm designed to recover from a single DRAM chip failure of the data signals. The x4 SDDC can be configured to correct errors in x4 chips or to correct errors in x8 chips. Data or data pin errors in the same chip are correctable. Double errors across two chips are detectable. The SxEC-DxED algorithm is similar to SEC-DED (x = number of bits, 4 or 8). Below is an x4 SDDC example of how bits are organized into words that will contain, at most, a single bit error in the case of a single device failure.

Intel® E7500 Chipset MCH x4 Intel® SDDC technology implementation

The Intel® E7500 Chipset MCH uses the x4 SDDC implementation that allows the memory system to detect and correct 1- to 4-bit internal data and data pin failures within one DDR memory device, and detects up to 8-bit internal data and data pin failures within two DDR memory devices. This implementation is designed to recover from faults that are contained within a single DDR memory device that do not impact other DDR memory devices in the memory system. This implementation cannot tolerate the failure of control signals or the failure to properly complete the JEDEC Mode Register Set (MRS) initialization of the DDR memory device.

Read the full Intel® E7500 Chipset MCH Intel® x4 SDDC Application Note.

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