Intel® E7500 Chipset Memory Controller Hub Datasheet

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Intel® E7500 Chipset Memory Controller Hub Datasheet

The Intel® E7500 chipset is targeted for the server market, both front-end and general purpose low- to mid-range. It is intended to be used with the Intel® Xeon® processor with 512-KB L2 cache. The E7500 chipset consists of three major components: the Intel® E7500 Memory Controller Hub (MCH), the Intel® I/O Controller Hub 3 (ICH3-S), and the PCI/PCI-X 64-bit Hub 2.0 (P64H2). The MCH provides the system bus interface, memory controller, hub interface for legacy I/O, and three high-performance hub interfaces for PCI/PCI-X bus expansion.

This document describes the E7500 Memory Controller Hub (MCH). “Intel® E7500 Chipset System Architecture” provides an overview of each of the components of the E7500 chipset. For details on other components of the chipset, refer to that component’s datasheet.

The MCH contains two sets of software accessible registers, accessed via the host processor I/O address space:
• Control registers – These registers are I/O mapped into the processor I/O space, which control access to PCI configuration space
• Internal configuration registers – These registers, which reside within the MCH, are partitioned into multiple logical device register sets (“logical” since they reside within a single physical device). One register set is dedicated to Host-HI Bridge functionality (controls PCI_A, DRAM configuration, other chipset operating parameters, and optional features).

Other sets of registers map to HI_B, HI_C and HI_D. The MCH supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism #1 in the PCI specification.

Read the full Intel® E7500 Chipset Memory Controller Hub Datasheet.