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Intel E77221 Chipset Datasheet
The Intel® E7221 chipset is targeted for the UP sub-value entry server market and consists of the following components: Memory Controller Hub (MCH), Intel® 6702PXH 64-bit PCI Hub (PCI Express x8 equivalent), and Intel® I/O Controller Hub 6 (ICH6). In addition, the MCH includes Integrated Graphics with standard SVGA capabilities. This document is the datasheet for the Intel® E7221 MCH. Topics covered include; signal description, system memory map, register descriptions, a description of the MCH interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics. Note: Unless otherwise specified, ICH6 refers to the Intel® 82801FB ICH6, 82801FR ICHR, 82801FW ICH6W, and 82801FRW ICH6RW I/O Controller Hub components. MCH Overview The MCH connects to the processor as shown in Figure 1-1. A major role of the MCH in a system is to manage the flow of information between its interfaces: the processor interface (FSB), the System Memory interface (DRAM controller), the Intel® 6702PXH 64-bit PCI Hub interface via PCI Express, and the I/O Controller Hub through the DMI interface. This includes arbitrating between the interfaces when each initiates transactions. The processor interface supports the Pentium® 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports up to two channels of DDR or DDR2 SDRAM. The MCH also supports the PCI Express* based Intel® 6702PXH 64-bit PCI Hub. Thus, the E7221 chipset is NOT compatible with AGP (1X, 2X, 4X, or 8X). To increase system performance, the MCH incorporates several queues and a write cache. The MCH also contains advanced power management logic.
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