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RS - Intel® Montara-GML Chipset GMCH and Montara-GM Chipset GMCH

Intel® 852GM/852GMV Chipset GMCH

Processor/Host Bus Support
• Intel® Celeron® processor (478-pin package) • Supports the processor subset of the Enhanced Mode Scalable bus protocol 2X Address, 4X data • Intel Celeron processor System Bus interrupt delivery • Mobile Intel® Pentium® 4 Processor-M (478-pin package) • Supports the subset of the Enhanced Mode Scalable bus protocol • Mobile Intel Pentium 4 Processor-M System Bus interrupt delivery • Supports system bus at 400-MHz or 3.2 GB/s • Supports host Dynamic Bus Inversion (DBI) • Supports 32-bit host bus addressing • 12-deep In- Order-Queue • AGTL+ bus driver technology with integrated AGTL termination resistors • Supports Enhanced Intel SpeedStep® technology • Intel® Celeron® M processor • 400-MHz front side bus frequency• Source synchronous double pumped address (2X) • Source synchronous quad pumped data (4X)• FSB interrupt delivery • Supports Host bus dynamic bus inversion (DBI) • Supports 32-bit host bus addressing • 8-deep in-order queue • AGTL+ bus driver technology with integrated AGTL+ termination resistors

Memory System
• Directly supports one DDR SDRAM channel, 64-bits wide • Supports 200/266-MHz DDR SDRAM devices with max of 2 Double-Sided SODIMMs (4 rows populated) with unbuffered PC1600/PC2100 DDR (Triangle Lists, Strips, and Fans support)• SDRAM (without ECC)• Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies providing maximum capacity of 1-GB with x16 devices and up to 2-GB with high density 512-Mbit technology• All supported devices have 4 banks • Supports up to 16 simultaneous open pages • Supports page sizes of 2-kB, 4-kB, 8-kB, and 16-kB. Page size is individually selected for every row (UMA support only)

System Interrupts
• Supports Intel 8259 and FSB interrupt delivery mechanism • Supports interrupts signaled as upstream Memory Writes from PCI and Hub Interface• MSI sent to the CPU through the System Bus

Read the full Intel® 852GM/852GMV Chipset GMCH Datasheet.