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Intel® 82801DB I/O, 82801DBL I/O Controller Hub 4-L Spec Update

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Intel® 82801DB I/O, 82801DBL I/O Controller Hub 4-L Spec Update

This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published. Note: All references to ICH4 refer to both ICH4 and ICH4-L, unless specified otherwise.

The following table indicates the Specification Changes, Errata, Specification Clarifications, or Documentation Changes that apply to the Intel® 82801DB I/O Controller Hub 4 (ICH4) and Intel® 82801DBL I/O Controller Hub 4-L (ICH4-L). Intel intends to fix some of the errata in a future stepping of the component(s), and to account for the other outstanding issues through documentation or specification changes as noted. 1. SMBus Arbitration Erratum

Problem: ICH4 will not detect a bus collision when attempting to STOP at the end of a SMBus transaction as a master. If there is another external Bus Master attempting to access the bus at the same time and wins the arbitration during STOP bit, ICH4 does not set the Bus Error bit.

Implication: A master attempting a transfer that had actually “lost” may think that its transaction was completed when it was not completed.

Workaround: None.

Status: There are no plans to fix this erratum. For the steppings affected, see the Summary Tables of Changes.

Read the full Intel® 82801DB I/O, 82801DBL I/O Controller Hub 4-L Specification Update.