Intel® 82801DB I/O Controller Hub 4 (ICH4) Datasheet
This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating ICH4-based products. Although some details of these features are described within this datasheet, refer to the individual industry specifications listed in Table 1-1 for the complete details.
Chapter 1. Introduction. Provides information on datasheet organization and introduces the ICH4.
Chapter 2. Signal Description. Provides a detailed description of each ICH4 signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals.
Chapter 3. ICH4 Power Planes and Pin States. Provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset.
Chapter 4. ICH4 and System Clock Domains. Provides a list of each clock domain associated with the ICH4 in an ICH4-based system.
Chapter 5. Functional Description. Provides a detailed description of the functions in the ICH4. All PCI buses, devices, and functions in this datasheet are abbreviated using the following nomenclature; Bus: Device: Function. This datasheet abbreviates buses as B0 and B1, devices as D8, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 5 is abbreviated as D31:F5, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the ICH4’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration.
Chapter 6. Register, Memory and I/O Address Maps. Provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the ICH4.
Chapter 7. LAN Controller Registers. Provides a detailed description of all registers that reside in the ICH4’s integrated LAN controller. The integrated LAN controller resides on the ICH4’s external PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0).
Chapter 8. Hub Interface to PCI Bridge Registers. Provides a detailed description of all registers that reside in the Hub Interface to PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0).
Chapter 9. LPC Bridge Registers. Provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the ICH4 including DMA, Timers, Interrupts, CPU Interface, GPIO, Power Management, System Management and RTC.
Read the full Intel® 82801DB I/O Controller Hub 4 Datasheet.