Intel® 7510/7512 Scalable Memory Buffer Spec Update
This document is an update to the specifications contained in
the Affected Documents table below. This document is a compilation of device and documentation errata, specification
clarifications and changes. It is intended for hardware system manufacturers and software developers of applications,
operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and
are no longer published in other documents. This document may also contain information that was not previously published.
The following tables indicate the errata, specification changes, specification clarifications, or documentation
changes which apply to Intel® 7510/7512 Scalable Memory Buffer. Intel may fix some of the errata in a future stepping of
the component, and account for the other outstanding issues through documentation or specification changes as noted. These
tables use the following notations:
1. On Intel® 7510/7512 Scalable Memory Buffer, JTAG - BScan EXTEST is non-
compliant to 1149.1 specification (uses wrong clock edge).
Problem: As per the JTAG 1149.1 specification, “test data
registers enabled to drive data off-chip shall be designed such that component outputs change only on the falling edge of
TCK after entry to the Update-DR, Update-IR, Run-Test/Idle or Test-Logic-Reset controller state as a result of signals
applied to TCK and TMS”. Intel® 7510/7512 Scalable Memory Buffer is in violation of this specification.
Implication: On
Intel® 7510/7512 Scalable Memory Buffer, while performing DFx Boundary Scan (EXTEST), system pins (including DDR, Intel®
Scalable Memory Interconnect (Intel® SMI) and misc IOs) are transmitted on the rising TCK edge (instead of falling TCK
edge).
Workaround: If using automated test equipment to sample the output data when executing EXTEST, the test must
wait for the rising edge of TCK before sampling the values being driven on the Intel® 7510/7512 Scalable Memory Buffer
output pins.
Status: No Fix.
Read the full Intel® 7510/7512 Scalable Memory Buffer Specification Update.
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Intel® 7510/7512 Scalable Memory Buffer Spec Update
This document is an update to the specifications contained in
the Affected Documents table below. This document is a compilation of device and documentation errata, specification
clarifications and changes. It is intended for hardware system manufacturers and software developers of applications,
operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and
are no longer published in other documents. This document may also contain information that was not previously published.
The following tables indicate the errata, specification changes, specification clarifications, or documentation
changes which apply to Intel® 7510/7512 Scalable Memory Buffer. Intel may fix some of the errata in a future stepping of
the component, and account for the other outstanding issues through documentation or specification changes as noted. These
tables use the following notations:
1. On Intel® 7510/7512 Scalable Memory Buffer, JTAG - BScan EXTEST is non-
compliant to 1149.1 specification (uses wrong clock edge).
Problem: As per the JTAG 1149.1 specification, “test data
registers enabled to drive data off-chip shall be designed such that component outputs change only on the falling edge of
TCK after entry to the Update-DR, Update-IR, Run-Test/Idle or Test-Logic-Reset controller state as a result of signals
applied to TCK and TMS”. Intel® 7510/7512 Scalable Memory Buffer is in violation of this specification.
Implication: On
Intel® 7510/7512 Scalable Memory Buffer, while performing DFx Boundary Scan (EXTEST), system pins (including DDR, Intel®
Scalable Memory Interconnect (Intel® SMI) and misc IOs) are transmitted on the rising TCK edge (instead of falling TCK
edge).
Workaround: If using automated test equipment to sample the output data when executing EXTEST, the test must
wait for the rising edge of TCK before sampling the values being driven on the Intel® 7510/7512 Scalable Memory Buffer
output pins.
Status: No Fix.
Read the full Intel® 7510/7512 Scalable Memory Buffer Specification Update.
