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Intel® 7500 Scalable Memory Buffer DatasheetIntel® 7500/7510/7512 Scalable Memory BufferOverviewIntel® 7500/7510/7512 Scalable Memory Buffer
supports DDR3 SDRAM main memory. It interfaces with the host memory controller via an Intel® Scalable Memory Interconnect (Intel® SMI) channel.Intel
7500/7510/7512 Scalable Memory Buffer is responsible for handling Intel SMI channel and memory requests to and from the local DIMM. All memory control for the
DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management.The Intel®7500
Scalable Memory Buffer is the first generation product of this memory buffer family; the Intel 7510 Scalable Memory Buffer adds greater memory capacity over its
predecessor while the Intel 7512 Scalable Memory Buffer is the low power version of Intel 7510 Scalable Memory Buffer.Intel® SMI functionalityIntel
7500/7510/7512 Scalable Memory Buffer provides a single Intel SMI interface, with the following functionality.• Intel SMI protocol and signaling includes
support for the following:-- 4.8 Gbps, 5.86 Gbps, 6.4 Gbps signaling forwarded clock fail-over Northbound (NB) and Southbound (SB).-- 9 data lanes plus
1 CRC lane plus 1 spare lane SB.-- 12 data lanes plus 1 CRC lane plus 1 spare NB.• Support for integrating RDIMM thermal sensor information into Intel
SMI Status Frame.• No support for daisy chaining (Intel 7500/7510/7512 Scalable Memory Buffer is the only Intel SMI device in the channel).• No support
for FB-DIMM1 protocol and signaling.Read the full Intel® 7500
Scalable Memory Buffer Datasheet.
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