Intel® 6300ESB I/O Controller Hub Datasheet
This datasheet is intended for Original Equipment Manufacturers (OEMs) and
BIOS vendors creating products based on the Intel® 6300ESB I/O Controller Hub (Intel® ICH). This manual assumes a working
knowledge of the vocabulary and principles of USB, IDE, AC’97, SMBus, PCI, ACPI, and LPC. Although some details of these
features are described herein, refer to the individual industry specifications listed in Table 1 for the complete
details.
Chapter 1, “Introduction” introduces the Intel® 6300ESB ICH and provides information on manual
organization.
Chapter 2, “Intel® 6300ESB ICH and System Clock Domains” provides a list of each clock domain associated
with the Intel® 6300ESB ICH in an Intel® 6300ESB ICH-based system.
Chapter 3, “Signal Description” provides a detailed
description of each Intel® 6300ESB ICH signal. Signals are arranged according to interface.
Chapter 4, “Intel® 6300ESB
ICH Power Planes and Pin States” provides a complete list of signals, their associated power well, their logic level in
each suspend state, and their logic level before and after reset.
Chapter 5, “Functional Description” provides a
detailed description of the functions in the Intel® 6300ESB ICH. All PCI buses, devices, and functions in this manual are
abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as
D8, D29, D30, and D31 and functions as F0, F1, F2, F3, F4, F5, F6, and F7. For example, Device 31 Function 5 is abbreviated
as D31:F5; Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and may be
considered to be Bus 0.
Chapter 6, “Register and Memory Mapping” provides an overview of the registers, fixed I/O
ranges, variable I/O ranges, and memory ranges decoded by the Intel® 6300ESB ICH.
Chapter 7, “Hub Interface to PCI
Bridge Registers (D30:F0)” provides a detailed description of all registers that reside in the Hub Interface to PCI bridge.
This bridge resides at Device 30, Function 0 (D30:F0).
Chapter 8, “LPC I/F Bridge Registers (D31:F0)” provides a
detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0).
This function contains registers for many different units within the Intel® 6300ESB ICH including DMA, Timers, Interrupts,
CPU Interface, GPIO, Power Management, System Management, and RTC.
Read the full Intel® 6300ESB I/O Controller Hub Datasheet.
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Intel® 6300ESB I/O Controller Hub Datasheet
This datasheet is intended for Original Equipment Manufacturers (OEMs) and
BIOS vendors creating products based on the Intel® 6300ESB I/O Controller Hub (Intel® ICH). This manual assumes a working
knowledge of the vocabulary and principles of USB, IDE, AC’97, SMBus, PCI, ACPI, and LPC. Although some details of these
features are described herein, refer to the individual industry specifications listed in Table 1 for the complete
details.
Chapter 1, “Introduction” introduces the Intel® 6300ESB ICH and provides information on manual
organization.
Chapter 2, “Intel® 6300ESB ICH and System Clock Domains” provides a list of each clock domain associated
with the Intel® 6300ESB ICH in an Intel® 6300ESB ICH-based system.
Chapter 3, “Signal Description” provides a detailed
description of each Intel® 6300ESB ICH signal. Signals are arranged according to interface.
Chapter 4, “Intel® 6300ESB
ICH Power Planes and Pin States” provides a complete list of signals, their associated power well, their logic level in
each suspend state, and their logic level before and after reset.
Chapter 5, “Functional Description” provides a
detailed description of the functions in the Intel® 6300ESB ICH. All PCI buses, devices, and functions in this manual are
abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as
D8, D29, D30, and D31 and functions as F0, F1, F2, F3, F4, F5, F6, and F7. For example, Device 31 Function 5 is abbreviated
as D31:F5; Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and may be
considered to be Bus 0.
Chapter 6, “Register and Memory Mapping” provides an overview of the registers, fixed I/O
ranges, variable I/O ranges, and memory ranges decoded by the Intel® 6300ESB ICH.
Chapter 7, “Hub Interface to PCI
Bridge Registers (D30:F0)” provides a detailed description of all registers that reside in the Hub Interface to PCI bridge.
This bridge resides at Device 30, Function 0 (D30:F0).
Chapter 8, “LPC I/F Bridge Registers (D31:F0)” provides a
detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0).
This function contains registers for many different units within the Intel® 6300ESB ICH including DMA, Timers, Interrupts,
CPU Interface, GPIO, Power Management, System Management, and RTC.
Read the full Intel® 6300ESB I/O Controller Hub Datasheet.
