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Intel® 5100 Memory Controller Hub Chipset Datasheet

Intel® 5100 Memory Controller Hub Chipset Datasheet

The Intel® 5100 Memory Controller Hub Chipset (Intel® 5100 MCH Chipset, formerly code-named San Clemente or SC) is designed for systems based on the Dual-Core Intel® Xeon® processor 5100 series, Quad-Core Intel® Xeon® processor 5300 series, Dual-Core Intel® Xeon® processor 5200 series, Quad-Core Intel® Xeon® processor 5400 series, and Intel® Core™2 Duo Processor T9400, and supports FSB operation of 1066 MT/s and 1333 MT/s. The Intel® 5100 MCH Chipset-based platforms contain two main components: the Memory Controller Hub (MCH) for the host bridge and the I/O Controller Hub (ICH) for the I/O subsystem. The Intel® 5100 MCH Chipset-based platform uses the Intel® 82801IR I/O Controller Hub (ICH9R).

The Intel® 5100 MCH Chipset is implemented in a 0.13 μm silicon process, packaged in a 1432 pin FCBGA package with integrated heat spreader. The balls are on 1.092 mm (43 mil) centers. The overall package dimensions are 42.5 mm by 42.5 mm. The Intel® 5100 MCH Chipset-based platform for Dual-Processor (DP) system designs supports a 771-land, FC-LGA4 (Flip Chip Land Grid Array 4) package for the Quad-Core and Dual-Core Intel® Xeon® Processor 5000 Sequence. This package uses the matching LGA771 socket. The surface mount, LGA771 socket supports Direct Socket Loading (DSL).

The Intel® 5100 MCH Chipset-based platform for Uni-Processor (UP) system design supports 479-ball Micro-FCBGA (Flip Chip Ball Grid Array) and 478-pin Micro-FCPGA (Flip Chip Pin Grid Array) packages for the Intel® Core™2 Duo Processor T9400.

Read the full Intel® 5100 Memory Controller Hub Chipset Datasheet.

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