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Intel® 3200 and 3210 Chipset: Datasheet


The Intel® 3200 and 3210 Chipsets are designed for use with the Dual-Core Intel® Xeon® Processor 3000 Series and Quad-Core Intel® Xeon® Processor 3200 Series in server platforms. The chipset contains two components: 3210/3100 MCH for the host bridge and I/O Controller Hub 9 (ICH9) for the I/O subsystem. The ICH9 is the ninth generation I/O Controller Hub and provides a multitude of I/O-related functions. Figure 1 and Figure 2 show example system block diagrams for the Intel® 3200 and 3210 Chipsets.

This document is the datasheet for the Intel® 3200 and 3210 Memory Controller Hub (MCH). Topics covered include: signal description, system memory map, PCI register description, a description of the MCH interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics.

MCH Overview

The role of a MCH in a system is to manage the flow of information between its four interfaces: the processor interface, the system memory interface, the PCI Express* interface, and the I/O Controller through DMI interface. This includes arbitrating between the four interfaces when each initiates transactions. It supports one or two channels of DDR2 SDRAM. It also supports the PCI Express-based external device attach. The Intel 3200/3210 Chipset platform supports the ninth generation Intel® I/O Controller Hub ICH9 (Intel ICH9) to provide I/O-related features.

Read the full Intel® 3200 and 3210 Chipset Datasheet.

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