The physics vertical segment includes code for solid-state physics (ZIB Ising 3D), fluid flow dynamics (NASA OVERFLOW), and radio astronomy (ASKAP tHogbomClean).
Intel measured as of May 2014
ZIB (Zuse-Institut Berlin)
Ising 3D (solid-state physics, simulate atoms, computes spin behavior in a 128x128x128 grid):
Host: 2 Intel® Xeon® processor E5-2670 (8 core, 2.6 GHz. 115 W), 64 GB memory, default BIOS settings
Coprocessor: ES2 B0, 61 core, 1.091 GHz, 8 GB at 5.5 GT/s)
Application: Ising 3D
Time: 0.0431 ns/update (2-socket Intel Xeon processor only); 0.0124 ns/update (1 Intel® Xeon Phi™ coprocessor)
Source: Intel Internal Testing
Platform hosting the coprocessor and platform for 2-socket Intel® Xeon® processor baseline:
Two-socket Intel® Software Development Platform: 2x Intel Xeon processor E5-2697 v2 (12 core, 30 MB cache, 2.7 GHz, 8.0 GT/s Intel® QuickPath Interconnect (Intel® QPI), 135W thermal design power (TDP), Intel® Turbo Boost Technology on, Intel® Hyper-Threading Technology on), 64 GB memory at 1600 MHz, Red Hat Enterprise Linux* (RHEL*) 6.4
Intel Xeon Phi coprocessor 7120A: 61 cores, 1.238 GHz, 16 memory channels, 16 GB Memory at 5.5 GT/s, 300 W TDP C-step (Intel Turbo Boost Technology on, error correcting code (ECC) on)
NVIDIA Tesla* K40c graphics processing unit (GPU), 2880 SP cores, 960 DP cores, 745 MHz (nominal) 875 MHz boost, 12 memory channels, 12 GB memory at 6.0 GT/s, ECC on, 235 W TDP
CUDA 5.5, (875 MHz boost frequency was enabled for result)
Software Stack (Intel Xeon Phi coprocessor):
Intel® Manycore Platform Software Stack (Intel® MPSS) 2.1.6720-121 (Flash*: 2.1.02.0386; Coprocessor OS: 220.127.116.11-g5f2543d)
Intel® C++ Composer XE 18.104.22.168, Intel® MPI Library 4.1.0.030
2-socket Intel Xeon Processor Score: 235.3 Clean rate in iterations/sec (higher is better)
2-socket Intel Xeon Processor + Intel Xeon Phi Coprocessor Score: 408.2 Clean rate in iterations/sec (higher is better)
2-socket Intel Xeon Processor + NVIDIA Tesla K40c Score: 283.3 Clean rate in iterations/sec (higher is better)
Source: Intel internal testing TR2060A
NASA OVERFLOW Version 2.2G
Platform hosting the coprocessor:
Two-socket Intel® Server board W2600CR software development platform: 2x Intel Xeon processor E5-2697 v2 (12 core, 30 MB cache, 2.7 GHz, 8.0 GT/s Intel QPI, 130 W TDP), 64 GB memory at 1600 MHz, RHEL
Intel Xeon Phi coprocessor 7120P: 61 cores, 1.238 GHz, 16 memory channels, 16 GB memory at 5.5 GT/s, 300 W TDP C-step (ECC on, Intel Turbo Boost Technology off)
Intel MPSS 6720-19
Intel MPI Library 4.1.040
2-socket Intel Xeon Processor Score: 142 seconds (lower is better)
Intel Xeon Phi Coprocessor (Native) Score: 317 seconds
2-socket Intel Xeon Processor + Intel Xeon Phi Coprocessor (Symmetric) Score: 118 seconds
Source: Intel Internal Testing TR2084
Additional information: 1 2 3 4 5
Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations, and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information, go to www.intel.com/performance.
Intel does not control or audit the design or implementation of third party benchmarks or websites referenced in this document. Intel encourages all of its customers to visit the referenced websites or others where similar performance benchmarks are reported and confirm whether the referenced benchmarks are accurate and reflect performance of systems available for purchase.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/content/www/us/en/processors/processor-numbers.html for details.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel® microprocessors. These optimizations include SSE2 and SSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel.
Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel® microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product user and reference guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
Different hardware architectures may require different source code. Results are based on Intel’s best efforts to use code optimized to run on all architectures and perform the same work. Future code optimizations may result in different results.
Microprocessor-dependent optimizations in this product are intended for use with Intel® microprocessors. Certain optimizations not specific to Intel® microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product user and reference guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804