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Intel® Xeon Phi™ Product Family

Power your breakthrough innovations with the highly parallel processing of the Intel® Xeon Phi™ coprocessor. We’ve packed over a teraFLOPS of double-precision peak performance into every chip.

Manufacturing Applications

The manufacturing vertical uses many software packages for static, dynamic, and structural analysis of a wide range of design problems. ANSYS Mechanical* is a widely used mechanical design software package, while MiniFE* is a finite element analysis tool.

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Configuration Details:

Intel measured as of December 2014

Open LB (Lattice Boltzmann Method) (Release olb-0.8r0)

Platform hosting the coprocessor & platform for two-socket Intel® Xeon® processor Baseline:

Two-socket Intel® Software Development Platform: two Intel Xeon processor E5-2697v2 (12Core, 30M cache, 2.7GHz, 8.0GT/s Intel QPI, 130W TDP, Intel® Turbo Boost Technology on, Intel® Hyper-Threading Technology on)  64GB Memory at 1600MHz, RHEL 6.2

Coprocessor Details:

Intel® Xeon Phi™ coprocessor 7120A: 61cores, 1.238GHz, 16 memory channels, 16GB Memory at 5.5GT/s, 300W TDP C-step (Intel Turbo Boost Technology on, error-correcting code (ECC) on)

Software Stack (Xeon Phi):

MPSS 3.3 (Flash: 2.1.02.0390; coprocessor OS: 2.6.38.8)

Intel® Composer XE 15.0.0.90, Intel MPI 5.0.1.035

Two-socket Xeon Score: 0.27 seconds (time/step, lower is better)

Two-socket Xeon + Xeon Phi Score: 0.179 seconds (time/step)

Source: Intel Internal Testing TR 2113

 

ANSYS* Mechanical (v15): (V145sp-5 Turbine SP5 Data Set)

Server with Intel® Xeon® E5-2670 Processors

Intel® Xeon Phi™ Coprocessor

Two 8-core 2.6 GHz E5-2670 (only 2 cores enabled for optimal performance vs. licensing costs)

64GB DDR3-1600, 8.0 GT/s, OS version 2.6.32-279.el6.x86_64, Intel Turbo Boost Technology enabled, Intel Hyper-Threading Technology disabled

7120A, 61-core 1.24 GHz, 16GB GDDR5-5500, 5.5 GT/s

Flash version 2.1.03.0386, SMC Firmware 1.15.4830, SMC Boot Loader Version: 1.8.4326, MPSS 2.1.6720-15, uOS version: 2.6.38.8-g2593b11

ECC enabled, Intel Turbo Boost Technology disabled

Intel® Composer XE 12.1, Intel® MPI Library 4.1.1.036 (Update 1)

Source: Intel Internal Testing TR 2083

 

Ansys Mechanical 16.0 (preview 4) in DMP Mode

Workload: V145sp-5 Static Structural Analysis 2.1M DOF

Platform Hosting the Coprocessor & platform for 2S Intel® Xeon® processor Baseline:

Two-socket Intel Software Development Platform: two Intel Xeon processor E5-2697v2 (12Core, 30M cache, 2.7GHz, 8.0GT/s Intel QPI, 130W TDP, Intel® Turbo Boost Technology on, Intel Hyper-Threading Technology on)  64GB Memory at 1600 MHz, RHEL 6.5 (4 MPI Processes; 1 Intel® Xeon® processor core used per MPI processes)

Coprocessor Details:

Intel® Xeon Phi™ coprocessor 7120P: 61cores, 1.238GHz,  16 memory channels, 16GB Memory@5.5GT/s, 300W TDP C-step (ECC off, Intel® Turbo Boost Technology on)

Software Stack:

MPSS 3.2

Intel Compiler 14.0 U2, Intel MKL 11.1.3, Intel MPI 4.1.3

 

2-socket Intel Xeon processor

2-socket Intel Xeon processor + one Intel Xeon Phi coprocessor

V145sp-5    

348 sec

43 Solve time (sec)(Lower is better)

Source: Intel Internal Testing TR2083A

 

Sandia Labs MiniFE Solver:

Platform hosting the coprocessor (& platform for two-socket Intel® Xeon® processor Baseline):

Two-socket Intel Software Development Platform: two Intel Xeon processor E5-2697v2 (12Core, 30M cache, 2.7GHz, 8.0GT/s Intel QPI, 130W TDP)  64GB Memory at 1600MHz, RHEL 6.4  Fabric: Mellanox MCX353A-FCAT FDR Infiniband 8x, firmware 2.30.3200

Coprocessor Details:

Intel® Xeon Phi™ coprocessor 7120A: 61cores, 1.238GHz, 16 memory channels, 16GB Memory at 5.5GT/s, 300W TDP C-step (Intel® Turbo Boost Technology off, ECC on)

Software Stack (Xeon Phi):

 MPSS 6720-16 (Flash: 2.1.03.0386; coprocessor OS: 2.6.38.8-g2593b11)

Intel Composer XE 14.0.0 (build 20130728), Intel MPI 4.1.1.036

MiniFE version 2.0, Results measured by Greg Skinner

 

2-socket Intel Xeon processor 

Intel Xeon Phi processor 

2-socket Intel Xeon processor + one Intel Xeon Phi coprocessor

2-socket Intel Xeon processor + two Intel Xeon Phi coprocessors

Mantevo MiniFE (200x200x200 grid) (1 node)

7.08

5.86

3.65

2.71 sec in total CG solver (lower is better)

Mantevo MiniFE (400x400x400 grid) (8 nodes)

  8.27

6.9

4.06 

3.32

Source: Intel Internal Testing TR 2049A

Additional information: 1 2 3 4 5

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Product and Performance Information

1

Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations, and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information, go to www.intel.com/performance.

2

Intel does not control or audit the design or implementation of third party benchmarks or websites referenced in this document. Intel encourages all of its customers to visit the referenced websites or others where similar performance benchmarks are reported and confirm whether the referenced benchmarks are accurate and reflect performance of systems available for purchase.

3

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/content/www/us/en/processors/processor-numbers.html for details.

4

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel® microprocessors. These optimizations include SSE2 and SSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel.

Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel® microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product user and reference guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

5

Different hardware architectures may require different source code. Results are based on Intel’s best efforts to use code optimized to run on all architectures and perform the same work. Future code optimizations may result in different results.

Microprocessor-dependent optimizations in this product are intended for use with Intel® microprocessors. Certain optimizations not specific to Intel® microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product user and reference guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804