EFI SMBus PPI Specification v0.9
Intel® Platform Innovation Framework for EFI SMBus PPI Specification Version 0.9.
This specification defines the
core code and services that are required for an implementation of the System Management Bus (SMBus) PEIM-to-PEIM Interface (PPI) of the Intel® Platform Innovation
Framework for EFI (hereafter referred to as the "Framework"). This PPI is used by other Pre-EFI Initialization Modules (PEIMs) to control an SMBus host
controller. This specification does the following:
• Describes the basic components of the PEI SMBus PPI
• Provides code definitions for the PEI SMBus PPI
and SMBus-related type definitions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
Data
Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-
order byte of a multi-byte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium®
processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use
“little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore
them when read. On an update operation, software must preserve any reserved field. April 1, 2004
Read the full EFI SMBus PPI Specification.
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EFI SMBus PPI Specification v0.9
Intel® Platform Innovation Framework for EFI SMBus PPI Specification Version 0.9.
This specification defines the
core code and services that are required for an implementation of the System Management Bus (SMBus) PEIM-to-PEIM Interface (PPI) of the Intel® Platform Innovation
Framework for EFI (hereafter referred to as the "Framework"). This PPI is used by other Pre-EFI Initialization Modules (PEIMs) to control an SMBus host
controller. This specification does the following:
• Describes the basic components of the PEI SMBus PPI
• Provides code definitions for the PEI SMBus PPI
and SMBus-related type definitions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
Data
Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-
order byte of a multi-byte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium®
processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use
“little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore
them when read. On an update operation, software must preserve any reserved field. April 1, 2004
Read the full EFI SMBus PPI Specification.
