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Intel® Platform Innovation Framework for EFI PCI Platform Support Specification

EFI Pre-EFI Initialization Core Interface Specification v0.91
Overview
This specification defines the core code and services that are required for an implementation of the Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This PEI Core Interface Specification (CIS) does the following:
• Describes the basic components of the PEI phase
• Provides code definitions for services and functions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
• Describes the machine preparation that is required for subsequent phases of firmware execution
• Discusses state variables that describe the system restart type (See Organization of the PEI CIS for more information)
Introduction
The Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework") is invoked quite early in the boot flow. Specifically, after some preliminary processing in the Security (SEC) phase, any machine restart event will invoke the PEI phase.
These PEIMs are responsible for the following:
• Initializing some permanent memory complement
• Describing the memory in Hand-Off Blocks (HOBs)
• Describing the firmware volume locations in HOBs
• Passing control into the Driver Execution Environment (DXE) phase
The PEI phase is also responsible for crisis recovery and resuming from the S3 sleep state. For crisis recovery, the PEI phase should reside in some small, fault-tolerant block of the firmware store. In addition, for a successful S3 resume, the speed of the resume is of utmost importance, so the code path through the firmware should be minimized. These two boot flows also speak to the need to keep the processing and code paths in the PEI phase to a minimum.
The implementation of the PEI phase is more dependent on the processor architecture than any other phase. In particular, the more resources the processor provides at its initial or near initial state, the richer the interface between the PEI Foundation and PEIMs. As such, there are several parts of the following discussion that note requirements on the architecture but are otherwise left architecturally dependent.
Read the full EFI Pre-EFI Initialization Core Interface Specification.

EFI Pre-EFI Initialization Core Interface Specification v0.91
Overview
This specification defines the core code and services that are required for an implementation of the Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This PEI Core Interface Specification (CIS) does the following:
• Describes the basic components of the PEI phase
• Provides code definitions for services and functions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
• Describes the machine preparation that is required for subsequent phases of firmware execution
• Discusses state variables that describe the system restart type (See Organization of the PEI CIS for more information)
Introduction
The Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework") is invoked quite early in the boot flow. Specifically, after some preliminary processing in the Security (SEC) phase, any machine restart event will invoke the PEI phase.
These PEIMs are responsible for the following:
• Initializing some permanent memory complement
• Describing the memory in Hand-Off Blocks (HOBs)
• Describing the firmware volume locations in HOBs
• Passing control into the Driver Execution Environment (DXE) phase
The PEI phase is also responsible for crisis recovery and resuming from the S3 sleep state. For crisis recovery, the PEI phase should reside in some small, fault-tolerant block of the firmware store. In addition, for a successful S3 resume, the speed of the resume is of utmost importance, so the code path through the firmware should be minimized. These two boot flows also speak to the need to keep the processing and code paths in the PEI phase to a minimum.
The implementation of the PEI phase is more dependent on the processor architecture than any other phase. In particular, the more resources the processor provides at its initial or near initial state, the richer the interface between the PEI Foundation and PEIMs. As such, there are several parts of the following discussion that note requirements on the architecture but are otherwise left architecturally dependent.
Read the full EFI Pre-EFI Initialization Core Interface Specification.

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