Bridge Resource Allocation Protocol is therefore specific to a particular chipset.
This specification does the following:
• Describes the basic components of the PCI Host Bridge Resource Allocation Protocol
• Describes several sample PCI architectures and a sample implementation of the PCI Host Bridge Resource Allocation Protocol
• Provides code definitions for the PCI Host Bridge Resource Allocation Protocol and the PCI-host-bridge-related type definitions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL does not describe platform policies. The platform policies are described by the EFI_PCI_PLATFORM_PROTOCOL and are outside the scope of this specification. The EFI_PCI_PLATFORM_PROTOCOL is defined in the Intel® Platform Innovation Framework for EFI PCI Platform Support Specification.
Data Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
Read the full EFI PCI Host Bridge Resource Allocation Protocol Specification.