EFI Memory Subclass Specification v0.9
Intel® Platform Innovation Framework for EFI Memory Subclass Specification, Version 0.9, April 1,
2004
Memory data hub subclass of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This specification does the
following:
• Describes the basic components of the memory data hub subclass and memory subclass data records
• Provides code definitions for type and record
definitions for the memory subclass that are architecturally required by the Intel Platform Innovation Framework for EFI Architecture Specification
• Provides
examples of the data records for the memory subclass
This specification complies with the System Management BIOS (SMBIOS) Reference Specification, version
2.3.4.
Data Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction
means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the
Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this
specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such
fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
Read the full EFI Memory Subclass Specification.
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EFI Memory Subclass Specification v0.9
Intel® Platform Innovation Framework for EFI Memory Subclass Specification, Version 0.9, April 1,
2004
Memory data hub subclass of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This specification does the
following:
• Describes the basic components of the memory data hub subclass and memory subclass data records
• Provides code definitions for type and record
definitions for the memory subclass that are architecturally required by the Intel Platform Innovation Framework for EFI Architecture Specification
• Provides
examples of the data records for the memory subclass
This specification complies with the System Management BIOS (SMBIOS) Reference Specification, version
2.3.4.
Data Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction
means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the
Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this
specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such
fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
Read the full EFI Memory Subclass Specification.
