EFI IDE Controller Initialization Protocol Specification v0.9
This specification defines the core code and services that are required for an implementation of the IDE Controller Initialization Protocol of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This protocol is used by an IDE bus driver to program an IDE controller and to obtain IDE device timing information. This protocol abstracts the nonstandard parts of an IDE controller. This protocol is not tied to any specific bus.
This specification does the following:
• Describes the basic components of the IDE Controller Initialization Protocol
• Provides code definitions for the IDE Controller Initialization Protocol and other IDE-controller-related type definitions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
Data Structure Descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
Read the full EFI IDE Controller Initialization Protocol Specification.