EFI Hot-Plug PCI Initialization Protocol Specification v0.9
This specification defines the core code and services that are required for an implementation
of the Hot-Plug PCI Initialization Protocol of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). A PCI bus driver,
running in the EFI Boot Services environment, uses this protocol to initialize the hot-plug subsystem. The same protocol may be used by other buses such as Card
Bus that support hot plugging. This specification does the following:
• Describes the basic components of the hot-plug PCI subsystem and the Hot-Plug PCI
Initialization Protocol
• Provides code definitions for the Hot-Plug PCI Initialization Protocol and the hot-plug-PCI–related type definitions that are
architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
Data Structure Descriptions
Intel®
processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-order byte of a multibyte data item in
memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium® processor family may be configured for
both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use “little endian” operation.
In some
memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore them when read. On an update operation,
software must preserve any reserved field.
Read the full EFI Hot-Plug PCI Initialization Protocol Specification.
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EFI Hot-Plug PCI Initialization Protocol Specification v0.9
This specification defines the core code and services that are required for an implementation
of the Hot-Plug PCI Initialization Protocol of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). A PCI bus driver,
running in the EFI Boot Services environment, uses this protocol to initialize the hot-plug subsystem. The same protocol may be used by other buses such as Card
Bus that support hot plugging. This specification does the following:
• Describes the basic components of the hot-plug PCI subsystem and the Hot-Plug PCI
Initialization Protocol
• Provides code definitions for the Hot-Plug PCI Initialization Protocol and the hot-plug-PCI–related type definitions that are
architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
Data Structure Descriptions
Intel®
processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low-order byte of a multibyte data item in
memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium® processor family may be configured for
both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use “little endian” operation.
In some
memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore them when read. On an update operation,
software must preserve any reserved field.
Read the full EFI Hot-Plug PCI Initialization Protocol Specification.
