EFI Data Hub Subclass Design Guide v0.9
Intel® Platform Innovation Framework for EFI Data Hub Subclass Design Guide, Version 0.9.
This
specification defines the core code and design guidelines that are required for an implementation of a new data hub subclass in the Intel® Platform Innovation
Framework for EFI (hereafter referred to as the "Framework"). This specification does the following:
• Describes basic interactions with the data hub
•
Defines the rules and guidelines for creating a new data hub subclass
• Provides code definitions for the data record subclass header and common macros that
are architecturally required by the Intel® Platform Innovation Framework for EFI
Architecture specification
This specification complies with the System
Management BIOS Reference Specification, version 2.3.4.
Data structure descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are
“little endian” machines. This distinction means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is
at the highest address. Processors of the Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All
implementations designed to conform to this specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked
reserved. Software must initialize such fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
April
1, 2004
Read the full EFI Data Hub Subclass Design Guide.
123KB
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EFI Data Hub Subclass Design Guide v0.9
Intel® Platform Innovation Framework for EFI Data Hub Subclass Design Guide, Version 0.9.
This
specification defines the core code and design guidelines that are required for an implementation of a new data hub subclass in the Intel® Platform Innovation
Framework for EFI (hereafter referred to as the "Framework"). This specification does the following:
• Describes basic interactions with the data hub
•
Defines the rules and guidelines for creating a new data hub subclass
• Provides code definitions for the data record subclass header and common macros that
are architecturally required by the Intel® Platform Innovation Framework for EFI
Architecture specification
This specification complies with the System
Management BIOS Reference Specification, version 2.3.4.
Data structure descriptions
Intel® processors based on 32-bit Intel® architecture (IA-32) are
“little endian” machines. This distinction means that the low-order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is
at the highest address. Processors of the Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All
implementations designed to conform to this specification will use “little endian” operation.
In some memory layout descriptions, certain fields are marked
reserved. Software must initialize such fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.
April
1, 2004
Read the full EFI Data Hub Subclass Design Guide.
