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Intel® Platform Innovation Framework for EFI CPU I/O Protocol Specification

EFI CPU I/O Protocol Specification v0.9

This specification defines the core code and services that are required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the "Framework"). This protocol provides an I/O abstraction for a system processor. This specification does the following:

• Describes the basic c...omponents
• Provides the CPU I/O interface code definitions for the CPU I/O Protocol and the related data types that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specifications

Data Structure Descriptions

Intel® processors based on 32-bit Intel® architecture (IA-32) are “little endian” machines. This distinction means that the low- order byte of a multibyte data item in memory is at the lowest address, while the high-order byte is at the highest address. Processors of the Intel® Itanium® processor family may be configured for both “little endian” and “big endian” operation. All implementations designed to conform to this specification will use “little endian” operation.

In some memory layout descriptions, certain fields are marked reserved. Software must initialize such fields to zero and ignore them when read. On an update operation, software must preserve any reserved field.

Read the full EFI CPU I/O Protocol Specification.

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