Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.
Intel MIC architecture will help create platforms running at trillions of calculations per second using fast and familiar Intel® Xeon® processors and co-processors based on the new architecture. The leap in processing speed is nothing short of exponential. As supercomputers have just recently broken the petaflop barrier, Intel already foresees many Intel MIC processors being combined to help partners break the next big milestone: the exaflop or 1,000 petaflop barrier.
Processing highly parallel workloads
The first Intel MIC products will target applications in High Performance Computing (HPC), Workstation, and Data Center segments that use highly parallel processing. The architecture utilizes a high degree of parallelism in smaller, lower power, and single threaded performance Intel processor cores, to deliver higher performance on highly parallel applications. While relatively few specialized applications today are highly parallel, these applications address a wide range of important problems ranging from climate change simulations, to genetic analysis, investment portfolio risk management, or the search for new sources of energy.
Standard programming models
A key advantage for developers using Intel MIC products is the ability to use standard, existing programming tools and methods. Intel MIC architecture combines many Intel CPU cores onto a single chip. These cores can be programmed using standard C, C++, and FORTRAN source code. The same program source code written for Intel Many Integrated Core products can be compiled and run on a standard Intel Xeon processor. The familiar programming model removes developer training barriers allowing the developer to focus on the problems rather than software engineering.
For example, CERN OpenLab, the European Organization for Nuclear Research, was able to use the Knights Ferry kit to migrate a complex benchmark written in C++ code to the new architecture in just a few days. According to Sverre Jarp, CTO of the CERN open lab, "The familiar hardware programming model allowed us to get the software running much faster than expected."
Creating a many core Intel architecture
The MIC project is the fruit of three research streams: The 80-core Tera-scale research chip program, the single-chip cloud computer initiative, and the Larrabee many-core visual computing project. The result is a fundamentally new architecture that uses the same tools, compilers, and libraries as the Intel Xeon processors. Since Intel processors are used in over 80% of the world’s supercomputers, programmers can continue to work in familiar territory when creating software for the MIC architecture.
Initial MIC products
The first MIC product is codenamed "Knights Corner," and development kits, codenamed "Knights Ferry," are already shipping to select software developers.
Knights Corner is the first product based on Intel MIC architecture, and targets HPC segments such as oil exploration, scientific research, financial analyses, and climate simulation, among many others. It will be made on Intel's 22-nanometer manufacturing process using transistor structures as small as 22 billionths of a meter, and will scale to more than 50 Intel processing cores on a single chip. Each core is smaller and lower-power and has a lower single-thread performance, but the aggregate performance is much higher. This hardware will help accelerate select highly parallel applications running on supercomputers powered by Intel Xeon processors.
Knights Ferry is a design and development kit that has been shipping to aid select software and hardware developers prepare for Knights Corner. In late 2010, Intel expanded the kit to include a broader range of developer tools for the Intel MIC architecture, allowing it to better work in concert with Intel Xeon processors and support diverse programming models.
Knights Ferry is already placing unprecedented performance in the hands of scientists, researchers, and engineers.