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See a server demonstration featuring Intel® Xeon® processor-based servers and Intel® Solid-State drives running Oracle TimesTen* In-Memory Database.
Intel® HD Graphics enables superior mainstream gaming and 3D experiences without the need for a discrete graphics card.
Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.
Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.
Presentation: Intel Developer Forum 2010, implementation guidelines for PCI Express* technology extensions.
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.
Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.
The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.
Intel helps define new serial ATA standards for faster and more efficient data transfer.
Intel® Rapid Storage Technology improves data reliability and delivers greater levels of performance, responsiveness, and expandability.
Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.
For laptop power management, Intel works with hardware manufacturers, developers, and vendors to create a framework that optimizes energy usage.
Presentation: Intel Developer Forum 2010, mobile platform idle power optimization - methodologies and tools.
Presentation: Intel Developer Forum 2010, interconnect bus extensions for energy efficient platforms.
The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.
User Agreement: legal terms that govern participant comments, suggestions and input during the high definition audio specification development.
Specification 0.92: defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.