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Intel® SSD Boosts Oracle TimesTen* In-Memory DB Performance Demo [64 K]
See a server demonstration featuring Intel® Xeon® processor-based servers and Intel® Solid-State drives running Oracle TimesTen* In-Memory Database.

See a server demonstration featuring Intel® Xeon® processor-based servers and Intel® Solid-State drives running Oracle TimesTen* In-Memory Database.

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Intel® HD Graphics Delivers Incredible Visuals [94 K]
Intel® HD Graphics enables superior mainstream gaming and 3D experiences without the need for a discrete graphics card.

Intel® HD Graphics enables superior mainstream gaming and 3D experiences without the need for a discrete graphics card.

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PHY Interface for the PCI Express* and USB SuperSpeed Architectures
Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

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Why PCI Express* Architecture for Graphics?
White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

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EFI PCI Platform Support Specification v0.9
PCI platform Support Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code and basic components.

PCI platform Support Protocol Specification for the Intel® Platform Innovation Framework for EFI defines the core code and basic components.

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Intel® Thunderbolt™ Technology Process Diagram [45 K]
Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

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PCI Express* [51 K]
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

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Device Guidelines for PCI Express* Technology Extensions
Presentation: Intel Developer Forum 2010, implementation guidelines for PCI Express* technology extensions.

Presentation: Intel Developer Forum 2010, implementation guidelines for PCI Express* technology extensions.

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PCI Express* Architecture Power Management Rev 1.1
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

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Intel® Universal Serial Bus Frequently Asked Questions (FAQ) [48 K]
Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.

Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.

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Universal Serial Bus EHCI Compliance Testing Program [44 K]
The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

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Serial ATA (SATA) [48 K]
Intel helps define new serial ATA standards for faster and more efficient data transfer.

Intel helps define new serial ATA standards for faster and more efficient data transfer.

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PHY Interface For the PCI Express* Architecture
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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Intel® Rapid Storage Technology [66 K]
Intel® Rapid Storage Technology improves data reliability and delivers greater levels of performance, responsiveness, and expandability.

Intel® Rapid Storage Technology improves data reliability and delivers greater levels of performance, responsiveness, and expandability.

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Intel® Many Integrated Core Architecture [74 K]
Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.

Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.

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Improved Laptop Power Management [49 K]
For laptop power management, Intel works with hardware manufacturers, developers, and vendors to create a framework that optimizes energy usage.

For laptop power management, Intel works with hardware manufacturers, developers, and vendors to create a framework that optimizes energy usage.

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Mobile Platform Idle Power Optimization ─Methodologies and Tools
Presentation: Intel Developer Forum 2010, mobile platform idle power optimization - methodologies and tools.

Presentation: Intel Developer Forum 2010, mobile platform idle power optimization - methodologies and tools.

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Interconnect Bus Extensions for Energy-Efficient Platforms
Presentation: Intel Developer Forum 2010, interconnect bus extensions for energy efficient platforms.

Presentation: Intel Developer Forum 2010, interconnect bus extensions for energy efficient platforms.

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Intel UDK2010 Firmware Developer Platform Kit
Guide: Explains the process of installing an Intel® UDK2010 firmware developer platform.

Guide: Explains the process of installing an Intel® UDK2010 firmware developer platform.

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Impact of
Presentation: Intel Developer Forum 2010, impact of “Idle” software on battery life.

Presentation: Intel Developer Forum 2010, impact of “Idle” software on battery life.

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PCI Express* Architecture [74 K]
The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

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PCI Express* Technology, Enterprise Serial Innovation
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

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High Definition Audio Specification
High Definition Audio Specification, revision 1.a: architecture, register/electrical interface, programming model, link protocol, codec features.

High Definition Audio Specification, revision 1.a: architecture, register/electrical interface, programming model, link protocol, codec features.

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High Definition Audio Specification Development Agreement
User Agreement: legal terms that govern participant comments, suggestions and input during the high definition audio specification development.

User Agreement: legal terms that govern participant comments, suggestions and input during the high definition audio specification development.

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EFI Human Interface Infrastructure Specification v0.9
Specification 0.92: defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

Specification 0.92: defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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