Intel's Packaging Databook Chapter 1: Introduction
Overview of Intel Packaging Technology
As semiconductor devices become significantly more complex, electronics designers are challenged to fully harness their computing power. Transistor count in products is expected to exceed 100 million. With a greater number of functions integrated on a die or chip of silicon, manufacturers and users face new and increasingly challenging electrical interconnect issues. To tap the power of the die efficiently, each level of electrical interconnect from the die to the functional hardware or equipment must also keep pace with these revolutionary devices. Package design has a major impact on device performance and functionality.
Today, submicron feature size at the die level is driving package feature size down to the design-rule level of the early silicon transistors. At the same time, electronic equipment designers are shrinking their products, increasing complexity, setting higher expectations for performance, and focusing strongly on reducing cost. To meet these demands, package technology must deliver higher lead counts, reduced pitch, and reduced footprint area, provide overall volume reduction, aid in system partitioning, and be cost-effective.
Circuit performance is only as good as the weakest link. Therefore, a significant challenge for packaging is to ensure it does not gate device performance. While packaging cannot add to the theoretical performance of the device design, it can have adverse effects if not optimized. Package performance, therefore, is the best compromise of electrical, thermal, and mechanical attributes, as well as the form factor or physical outline, to meet product-specific applications, reliability, and cost objectives.
Read the full Intel's Packaging Databook, Ch. 1.
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Intel's Packaging Databook Chapter 1: Introduction
Overview of Intel Packaging Technology
As semiconductor devices become significantly more complex, electronics designers are challenged to fully harness their computing power. Transistor count in products is expected to exceed 100 million. With a greater number of functions integrated on a die or chip of silicon, manufacturers and users face new and increasingly challenging electrical interconnect issues. To tap the power of the die efficiently, each level of electrical interconnect from the die to the functional hardware or equipment must also keep pace with these revolutionary devices. Package design has a major impact on device performance and functionality.
Today, submicron feature size at the die level is driving package feature size down to the design-rule level of the early silicon transistors. At the same time, electronic equipment designers are shrinking their products, increasing complexity, setting higher expectations for performance, and focusing strongly on reducing cost. To meet these demands, package technology must deliver higher lead counts, reduced pitch, and reduced footprint area, provide overall volume reduction, aid in system partitioning, and be cost-effective.
Circuit performance is only as good as the weakest link. Therefore, a significant challenge for packaging is to ensure it does not gate device performance. While packaging cannot add to the theoretical performance of the device design, it can have adverse effects if not optimized. Package performance, therefore, is the best compromise of electrical, thermal, and mechanical attributes, as well as the form factor or physical outline, to meet product-specific applications, reliability, and cost objectives.
Read the full Intel's Packaging Databook, Ch. 1.
