PCI Express* 3.0: PHY Implementation for Intel Platforms
Agenda
• Problem statement
• Existing usage of K-Code in 8b/10b
• Encoding scheme
• Transmitter equalization and training
• Implementation considerations
• Summary problem statement
• PCI Express* (PCIe*) 3.0 data rate decision: 8 GT/s, High Volume Manufacturing channel for client/servers
• Same channels and length for backwards compatibility
• Low power and ease of design; avoid using complicated receiver equalization, and so on
• Requirement: Double bandwidth from Gen 2, PCIe 1.0a data rate: 2.5 GT/s; PCIe 2.0 data rate: 5 GT/s
• Doubled the data rate/bandwidth from Gen 1 to Gen 2; data rate gives us a 60% boost in bandwidth; rest will come from encoding
• Replace 8b/10b encoding with a scrambling-only encoding scheme when operating at PCIe 3.0 data rate
• Double B/W: Encoding efficiency 1.25 x data rate 1.6 = 2x
Read the full PCI Express* 3.0 Presentation.
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PCI Express* 3.0: PHY Implementation for Intel Platforms
Agenda
• Problem statement
• Existing usage of K-Code in 8b/10b
• Encoding scheme
• Transmitter equalization and training
• Implementation considerations
• Summary problem statement
• PCI Express* (PCIe*) 3.0 data rate decision: 8 GT/s, High Volume Manufacturing channel for client/servers
• Same channels and length for backwards compatibility
• Low power and ease of design; avoid using complicated receiver equalization, and so on
• Requirement: Double bandwidth from Gen 2, PCIe 1.0a data rate: 2.5 GT/s; PCIe 2.0 data rate: 5 GT/s
• Doubled the data rate/bandwidth from Gen 1 to Gen 2; data rate gives us a 60% boost in bandwidth; rest will come from encoding
• Replace 8b/10b encoding with a scrambling-only encoding scheme when operating at PCIe 3.0 data rate
• Double B/W: Encoding efficiency 1.25 x data rate 1.6 = 2x
Read the full PCI Express* 3.0 Presentation.
