The second in a family of volume server chipsets, the Intel® E7501 chipset supports dual-processor (DP) server systems optimized for the Intel® Xeon® processor. The Intel E7501 chipset design delivers maximized system bus, memory and I/O bandwidth to enhance performance, scalability and end-user productivity while providing a smooth transition to next-generation server technologies.
Product information
File Type/Size: PDF 335KB
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| Features and benefits | |
|---|---|
| Supports 2 Intel® Xeon® processors with 512 KB L2 cache for dual-processing server systems | Delivers a platform that brings Intel NetBurst® microarchitecture and the Hyper-Threading Technology of the Intel® Xeon® processor to deliver best-in-class performance for peak server workloads. |
| 533 MHz system bus capability | Supports a high-performance platform by enabling a 4.3 GB/s system bus bandwidth that can support greater memory and I/O bandwidths. |
| Intel® Hub Architecture 2.0 connection to the MCH | This point-to-point connection between the MCH and the 3 Intel® 82870P2 controller hub devices provides greater than 1 GB/s of bandwidth. Error Correction Code (ECC) protection, coupled with high data transfer rates, support I/O segments with greater reliability and faster access to high-speed networks. |
| Intel® 82870P2 controller hub | Introduces next-generation PCI/PCI-X performance and significantly enhances platform flexibility. Two independent 64-bit, 133 MHz PCI-X segments and 2 hot-plug controllers (1 per segment) for each Intel 82870P2 controller hub device allow up to 6 PCI-X buses per system. |
| Dual-channel DDR-266 memory interface | Offers a maximum memory bandwidth of 4.3 GB/s through a 144-bit wide, 266 MHz Double Data Rate (DDR) SDRAM memory interface with densities up to 512 megabits. |
| Advanced platform RASUM | Provides a more reliable platform with features such as memory Error Correction Code (ECC) with Intel® x4 Single Device Data Correction1, hardware memory scrubbing, MCH SMBus target interface, hub interface ECC, and the availability of enhanced error status information maintained through reset. |
Additional information: 1
Technical Documents
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Intel® E7501 Chipset MCH...
Contains E7501 MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and...
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Intel® 82870P2 P64H2...
Intel® 82870P2 PCI/PCI-X 64-bit Hub 2: chip bridges PCI functions between hub interface, PCI Bus.
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Intel® 82801CA I/O...
Intel® 82801CA I/O Controller Hub 3-S: PCI bus interface, integrated LAN/IDE controllers, power...
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Intel® Xeon® Processor,...
Intel® Xeon® processor, Intel® E7500 Chipset compatible platform uniprocessor, angled and single channel...
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Intel® Xeon® and...
Covers component layout, baseboard requirements, and more for the Intel® Xeon® processor and Intel®...
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Intel® 82870P2 PCI/PCI-X...
Packaging technology, thermal specifications and metrology, and solutions for the Intel® 82870P2...
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Intel® E7500/E7501/E7505...
Thermal Design Guide: Intel® E7500/E7501/E7505 chipset MCH components.
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Spec Update, Intel®...
Specification Update, 2006: Intel® 82801CA I/O Controller Hub 3 (ICH3-S).
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Spec Update, Intel®...
Intel® 82870P2 PCI/PCI-X 64-bit Hub 2update covers document changes, errata, specification changes and...
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Intel® E7500 Chipset...
Specification Update, 2002: Intel® E7500 Chipset Memory Controller Hub.
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| Packaging information | |
The Intel® E7501 Chipset Memory Controller Hub (MCH) File Type/Size: PDF 2341KB |
1005-pin Flip Chip-Ball Grid Array (FC-BGA) |
Intel® 82801CA Integrated Controller Hub File Type/Size: PDF 1610KB |
421-pin Ball Grid Array (BGA) |
Intel® 82870P2 64-bit PCI/PCI-X controller File Type/Size: PDF 2193KB Intel(R) 82801CA I/O Controller Hub 3 (ICH3-S) Specification Update |
567-pin Flip Chip-Ball Grid Array (FC-BGA) |


